Synopsys DesignWare IP for PCIe 6.0 Complete IP Solution for PCIe 6.0

Synopsys, Inc. announced a complete IP solution for the PCIe 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 (SoC) designs.

Built on the company‘ widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the DesignWare IP for PCIe 6.0 supports the latest features in the standard spec including, 64GT/s PAM-4 signaling, FLIT mode and L0p power state. The complete IP solution addresses evolving latency, bandwidth and power-efficiency requirements of high-performance computing, AI and storage SoCs.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCIe 6.0 utilizes a MultiStream architecture, delivering up to 2x the performance of a single-stream design. The controller, with available 1,024-bit architecture, allows designers to achieve 64GT/s x16 bandwidth while closing timing at 1GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated test bench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

The firm‘ DesignWare PHY IP for PCIe 6.0 provides adaptive DSP algorithms that optimize analog and digital equalization to maximize power efficiency regardless of the channel. The PHY enables near zero link downtime using patent-pending diagnostic features. The placement-aware architecture of the DesignWare PHY IP for PCIe 6.0 minimizes package crosstalk and allows dense SoC integration for x16 links. The optimized data path with ADC-based architecture achieves low latency.

“Advanced cloud computing, storage and ML applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems,” said John Koeter, SVP, marketing and strategy, IP. “With Synopsys’ complete DesignWare IP solution for PCIe 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys’ proven expertise and established leadership in PCIe to accelerate their path to silicon success.“

“PCIe is the most widely-adopted and extensible interconnect technology in history,” said Jim Pappas, director, technology initiatives, Intel Corp. “Synopsys’ latest DesignWare IP for PCIe 6.0 is a leading indicator of the global ecosystems’ ongoing commitment to this important industry standard and sets the stage for PCIe Gen 6 development and adoption on future Intel platforms.“

The DesignWare Controller and PHY IP for PCIe 6.0 early access are scheduled to be available in 3Q21. The Verification IP for PCIe 6.0 is available.