PCI-SIG DevCon Taiwan: Astera Labs Demos PCIe 5.0 System Deployment in Collaboration With Intel and Synopsys
With Smart Retimer 32GT/s retimer SoC designed to PCIe 5.0 spec, doubles signal reach and achieves plug-and-play interoperation without compromising interconnect topologies even at 32 GT/s speeds.
This is a Press Release edited by StorageNewsletter.com on October 28, 2019 at 1:36 pmAstera Labs Inc., in collaboration with Synopsys, Inc., and Intel Corp., announced the demonstration of a complete PCIe 5.0 system, delivering 32GT/s speeds for next-gen server workloads.
The end-to-end solution showcases system-level multi-vendor interoperability between Intel’s PCIe 5.0 test chip, Synopsys’ silicon DesignWare Controller and PHY IP for PCIe 5.0, and Astera Labs’ Smart Retimer SoC for PCIe 5.0.
The companies will demonstrate the solution at the PCI-SIG Developers Conference in Taipei, Taiwan, October 28-29.
“We’re excited to collaborate with Synopsys and Intel to prove to the industry that we are ready for PCIe 5.0 customers and we are actively sampling our retimer SoC now,” said Jitendra Mohan, CEO, Astera Labs. “We’ve delivered the world’s first PCIe 5.0 Smart Retimer that provides backwards compatibility, enabling developers to future-proof their systems by leveraging the solution for PCIe 4.0 now and having a pin-compatible solution for PCIe 5.0 when systems are available in 2020. Collaborating with Synopsys and Intel helped accelerate our development process.“
“Synopsys, Astera Labs, and Intel are collaborating to help the PCIe ecosystem to meet their advanced requirements for networking, storage, and ML applications that require extremely high-speed interfaces,” said John Koeter, VP, marketing, IP, Synopsys. “By providing a complete IP solution for PCIe 5.0, Synopsys enables companies like Astera Labs to get an early start on their designs and benefit from Synopsys’ proven expertise in PCIe to achieve first-pass silicon success for their SoCs.“
“PCIe 5.0 technology adoption is crucial as the industry adds accelerated, heterogenous computing architectures and workload-optimized platforms to support the next gen of data-centric platform,” said Jim Pappas, director, technology initiatives, Intel. “Intel is a staunch proponent of PCIe 5.0 architecture and we are racing to deliver robust solutions that deliver faster speeds and lower latency to meet data centric workload requirements. We are pleased to collaborate with Astera Labs and Synopsys on pioneering this new ecosystem.“
The joint PCIe 5.0 demonstration will be showcased in the Synopsys booth at PCI-SIG DevCon Taipei, Taiwan, October 28-29 at the Taipei Marriott Hotel.
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