Everspin Design Guide for Using 1Gb STT-MRAM With Xilinx DDR4 FPGA Controller

Everspin Technologies, Inc. announced a design guide to streamline the integration of its 1Gb Spin-transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) product in the storage marketplace.

Xilinx, Inc. has been supporting STT-MRAM for 2 generations and enables the 1Gb STT-MRAM solution using its DDR4 controller in the Xilinx Vivado development environment.

The two companies integrated solution provides benefits, with the design guide and tools structured to address:

• Timing: Reducing operating frequency, increasing row access timing, increasing counter widths and reducing CAS page sizes

• Power-Up: Enabling anti-scribble mode during calibration

• Power-Down: Scramming or moving all relevant data into the persistent memory array

• Performance: Increasing pipeline depth and data transfer efficiency

• Scripts: Providing Verilog models and other detailed information to get storage OEM’s design up and running effectively

“MRAM and persistent memory is an increasingly important technology across a broad range of solutions,“ said Jamon Bowen, director, planning and storage segment, data center group, Xilinx. “We see many applications where advanced capabilities like power loss protection is critical. It’s exciting to see partners like Everspin make it easy for customers to develop world-class memory sub-systems leveraging the Xilinx platform.“

STT-MRAM devices allow enterprise infrastructure and data center providers to increase the reliability and performance of systems where performance data persistence is critical. This is achieved by delivering protection against power loss without the use of supercapacitors or batteries. In addition, the 1Gb part offers more effective management of I/O streams, creating a greater level of latency determinism and allowing storage OEMs to improve quality of service of their products. Similar benefits can also be achieved using the 1Gb STT-MRAM device as a persistent data write buffer in storage and fabric accelerators, computational storage, and other applications.

“We value our partnership with Xilinx and continue to collaborate with them to bring our STT-MRAM solutions to market,“ said Troy Winslow, VP, sales and marketing, Everspin. “Providing this design guide and tools will help streamline integration and time to market for our customers in providing enhanced applications for data centers.“

Resource:
Everspin ST-DDR4 Design Guide for Xilinx FPGA controllers
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