Everspin Expands STT-MRAM Ecosystem Support for 1Gb STT-MRAM With Cadence Design and Verification IP

Everspin Technologies, Inc. is expanding the ecosystem for its 1GB Spin-transfer Torque MRAM (STT-MRAM) with Cadence Design Systems, Inc. providing DDR4 Design IP (DIP) and Verification IP (VIP) support for 1GB STT-MRAM memory.

The two companies have collaborated together on multiple projects, and Cadence has supported STT-MRAM products since 2012.

With controller IP and VIP solutions, the customers will be able to request MRAM-enabled IP and VIP for their custom ASIC solutions.

STT-MRAM product family includes both 8-bit and 16-bit DDR4 compatible (ST-DDR4) interface versions of the device and are available in a JEDEC-compliant BGA package.

“Our customers are inquiring about DIP and VIP support, so they can create new ASIC solutions which will support Everspin STT-MRAM,” said Rizwan Ahmed, VP marketing, Everspin. “Everspin’s growing ecosystem is now supported by Cadence controller IP and VIP solutions, which are used broadly in storage systems.“

STT-MRAM 1GB part offers more effective management of I/O streams, creating a greater level of latency determinism and allowing storage OEMs to improve QoS of their products. Customers requiring DIP and VIP support to enable It can now work with Cadence to achieve it.

“The compatibility of Cadence DIP and VIP with Everspin’s STT-MRAM will provide systems developers the ability to implement a high-speed, persistent memory host controller and PHY in advanced SoCs,” said David Peña, director, product management, VIP, Cadence. “We are pleased to be working with Everspin to bring advanced persistent memory capability to modern data center storage and computing applications.“

The Cadence IP portfolio supports the company’s ‘Intelligent System Design’ strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. Customers benefit from having access to a complete, single-vendor solution for controller, PHY and VIP that speeds chip integration time and reduces interoperability risk.