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Teledyne LeCroy Extends CrossSyncPHY Technology to Support PCIe 5.0 Card ElectroMechanical Form Factor

Interposer enables integrated protocol and electrical debug at 32GT/s

Teledyne LeCroy, Inc. the extends its patented CrossSyncPHY technology to support the PCIe 5.0 Card Electromechanical (CEM) spec.

Teledyne Lecroy Crosssyncphy Technology To Support The Pcie 5.0 Card Electromechanical 1

This CEM interposer (PE230UIA-X) joins the existing CrossSync PHY enabled M.2 form factor interposers (PE210UIA for PCIe 4.0 and the PE222UIA for PCIe 5.0), with more form factors in development to fill out the portfolio of cross-layer probing.

Engineers at the leading edge of high-speed serial communications are validating, debugging and deploying the first gen of PCIe 5.0 devices for storage, networking and other applications. Device and interoperability problems often arise in the electrical domain, protocol interaction or a combination of the two. CrossSync PHY technology provides engineers the complete picture when testing the PCIe interface standard. By linking the oscilloscope with a protocol analyzer, it permits the oscilloscope and protocol analyzer traces to be viewed, navigated and analyzed in a time-correlated way during a single system test – a capability that is unique to the company. This capability allows problems to be quickly identified in a live link, speeding time-to-market for these new devices. All CrossSync PHY-enabled interposers operate with the firm’s PCIe protocol analyzers and LabMaster and WaveMaster oscilloscopes.

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Teledyne Lecroy Crosssyncphy Technology To Support The Pcie 5.0 Card Electromechanical 2

This new interposer brings CrossSync PHY capability to the industry standard CEM spec form factor at the full PCIe 5.0 rate of 32GT/s. This interposer includes probing points for reference clock, sideband signal, and power rail voltage and current monitoring, in addition to data signals for the protocol analyzer. Optional upgrades add oscilloscope probing points for all high-speed data signals.

Complex dynamic equalization algorithms, signal integrity challenges and the emergence of protocol-controlled system management interfaces increase the challenges of debugging problems in systems with high-speed serial data signals. Enabling engineers to see both the physical and protocol layers in a single, time-correlated window is a big step in making their job easier,” said Kevin Prusso, VP and GM. “We are pleased to extend our CrossSync PHY technology to the widely deployed CEM form factor to help engineers improve time-to-market, performance and reliability of their new designs.

All products are available for order.

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