OCP Global Summit 2026: Astera Labs Announces Aries 7, Industry’s First PCIe 7 Signal Conditioning Portfolio Across Copper and Optical Interconnects

Summary:

• Most comprehensive PCIe signal conditioning portfolio: Building on Aries’ field-tested deployments, Aries Smart Signal Conditioning family is now the industry’s first PCIe 7 portfolio to span copper and optical interconnects including retimers, redrivers, cable modules, optical drivers, and optical TIAs
• PCIe 7 connectivity from chip-to-chip, box-to-box, and rack-to-rack: Aries 7 portfolio is designed to enable PCIe 7 connectivity across chip-down solutions, smart cable modules including near package optics (NPO), linear pluggable optics (LPO), and copper – giving customers the flexibility to optimize for reach, power and density for each link in an AI cluster
• Smart, unified link intelligence: Advanced fleet management and deep diagnostics across Aries 7 portfolio is unified under the COSMOS software suite for ease of monitoring, debugging, and dynamic tuning – accelerating time-to-market and improving utilization for deployment at scale

Astera Labs, Inc., a player in semiconductor-based connectivity solutions for rack-scale AI infrastructure, announced the industry’s broadest PCIe 7 signal conditioning portfolio spanning smart retimers, redrivers, cable modules, optical drivers, and optical TIAs.The expanded Aries 7 portfolio offers hyperscalers, neoclouds, OEMs and ODMs a comprehensive connectivity platform that now extends reach from centimeters of PCB trace to 50+ meters over optical cables spanning multiple racks.

Multi-rack AI clusters are demanding more bandwidth between every accelerator, memory pool, and networking port. Yet doubling PCIe data rates shrinks signal margins, where a single unstable link can idle costly accelerators that reduce token-per-watt performance. And getting these platforms to production has meant stitching together fragmented multi-vendor solutions with different firmware and software, then re-spinning board designs and validation – resulting in delays in deploying AI infrastructure.

Aries has long been the gold standard for reliable PCIe links resulting in high accelerators’ utilization. The Aries PCIe 7 expansion carries that same philosophy across every channel a modern cluster needs: use copper where it is the most efficient choice and move to optical where reach demands it – all optimized and monitored through Astera Labs’ unified COSMOS software suite. Aries 7 Smart Retimers and Smart Redrivers support the OCP Signal Conditioner Standard Footprint, allowing customers to design once and decide later: as design requirements change, customers can pick different signal conditioners without redesigning the board – optimizing for power and accelerating time-to-market. Aries 7 Smart Optical Drivers and Optical TIAs enable that same intelligence in low power, high density NPO and LPO, designed to deliver optimum performance across multi-rack AI fabrics.

Platform partners have put Aries link reliability to the test across multiple generations: AMD and Intel have each validated Aries Smart Retimers in production across their platforms from PCIe 4 through 6. Both companies are now collaborating with Astera Labs to lead the industry’s transition to PCIe 7.

“The real question for architects isn’t retimer vs redriver, or copper vs optical: it’s whether they have one comprehensive toolbox with the optionality to pick the right tool for their evolving reach, density and power requirements” said Adit Narasimha, SVP, signal connectivity group, Astera Labs. “That is what we built with Aries: the same intelligence and the same software, for the solution the link needs.”

Aries 7 Smart Retimers, Smart Redrivers, Smart Cable Modules, and Smart Optical Driver and TIAs are expected to begin sampling in Q4 2026 to select hyperscale, OEM, and NPO customers, with broader availability anticipated as platforms complete qualification. Astera Labs will showcase PCIe 7 copper and optical demonstrations next week at the 2026 Open Compute Project (OCP) Global Summit, Oct. 12-15 in San Jose.

“As AI infrastructure grows across servers and racks, customers need open connectivity options that work with their platform designs. AMD is advancing a broad portfolio of compute and connectivity technologies, and we work with ecosystem partners such as Astera Labs to help customers build flexible, interoperable AI systems,” said Raghu Nambiar, Corporate Vice president, Data Center Ecosystems and Solutions, AMD.

“As systems continue to scale, reliable high-speed connectivity is essential to keeping compute resources efficiently utilized. Intel’s collaboration with Astera Labs builds on multiple gens of PCIe retimer validation and extends that proven interoperability toward PCIe 7, helping customers design scalable platforms with greater confidence and flexibility,” said Srini Krishna, fellow, data center group, Intel.

“Linear optics works at scale only if the electrical and optical halves of the link are designed together from the start. Pairing our photonic engines with Astera Labs’ Aries 7 Smart Optical Driver and TIA lets us hit the reach and density targets that multi-rack AI fabrics need, without the power and latency penalties of a retimed optical module,” said Matt Sysak, CTO, Lumentum.

“An AI cluster is only as strong as its weakest link six months into deployment. Astera Labs’ Aries 7 Smart Optical Driver and TIA let us build optical connectivity solutions with links that hold their signal integrity over the full life of a deployment, not just on Day One. That resilience, combined with enabling consistent performance across every unit we build, gives hyperscalers the confidence to qualify our solutions once and scale them across their fleet,” said Samuel Liu, VP, product, Lumilens.

“The OCP Signal Conditioner Standard Footprint was built to be protocol-agnostic, and extending it from Taurus’s Ethernet and UALink applications to the Aries PCIe portfolio is exactly the kind of industry-wide adoption we hoped to see. One common footprint spanning multiple protocols means hyperscalers can design their boards once and rely on multi-vendor sourcing as their fabrics evolve, instead of re-solving the same integration problem for every new interconnect,” said Zane Ball, CTO, Open Compute Project.