Astera Labs Bolsters Leo Smart Memory Controller Family for Agentic AI and General-Purpose Cloud Workloads

Summary:

• New Leo X-Series optimizes token economics: Paired with Astera Labs’ Scorpio X-Series Fabric Switches, Leo X-Series enables fabric-attached memory for long-context, KV-cache-intensive workloads. Platform-specific interfaces and customizable features improve inference performance with up to 62% faster time to first token (TTFT) and up to 22% more tokens per second (TPS)
• New Leo 2 E-Series and P-Series address CPU-attached capacity and rack-scale memory: The expanded Leo family supports CPU-attached DDR4 & DDR5 memory expansion with PCIe 6, single x16 and dual x8 host connectivity and CXL 3.2 support. The new E & P-Series Smart Memory Controllers double memory bandwidth and capacity vs. the previous generation
• Reliable memory reuse improves infrastructure TCO: Hyperscale-grade RAS, memory-health management, on-chip hardware engines, and automated repair enable reliable reuse of previously deployed DDR4 DIMMs alongside DDR5 memory in new, high-volume cloud server fleets
• Growing customer engagement and design-win momentum: The expanded Leo family is driving increased design activity and new design wins across a broadening set of AI labs, hyperscale and neocloud customers

 Astera Labs, Inc., a player in semiconductor-based connectivity solutions for rack-scale AI infrastructure, announced three new memory connectivity solutions – Leo X-Series and the Leo 2 E & P-Series -extending its hyperscale-proven Leo Smart Memory Controller family across direct fabric-attached GPU memory and CPU-attached expansion and pooled/shared memory architectures.New Leo X-Series: direct fabric-attached memory for agentic AI
The new Leo X-Series is a fabric-attached Smart Memory Controller purpose-built to directly support AI accelerator-side memory demand. Paired with Astera Labs’ Scorpio fabric switches, using PCIe and platform-specific protocols for scaling up GPUs, Leo X-Series enables direct connectivity to AI fabrics and a dedicated memory tier for offloading KV cache and agent context. As context windows grow and multi-turn sessions retain more prior tokens, larger KV-cache capacity with low-latency and high bandwidth access becomes critical for the highest-value agentic AI inference workloads, helping minimize response times and deliver a more responsive user experience.

By connecting memory directly to the scale-up fabric, Leo X-Series provides a lower-latency and higher bandwidth path for GPU-to-KV-cache access vs. architectures that rely solely on CPU-attached memory or NVMe storage tiers. Leo X-Series’ support for PCIe in addition to platform-specific custom interfaces allows hyperscalers and AI platform providers to build a customized memory companion architecture suited to their compute platform rather than a one-size-fits-all design. These capabilities are designed to improve KV-cache performance and token economics, delivering up to 62% lower TTFT and up to 22% more TPS.

Enhanced Leo 2 E-Series and Leo 2 P-Series for memory expansion and pooling/sharing
The enhanced Leo 2 E & P-Series provide complementary approaches to CPU-attached capacity and rack-scale memory utilization that can support AI agents, in-memory databases, and general-purpose cloud workloads. These devices support four DDR4 or DDR5 memory controllers that double memory bandwidth and capacity vs. the previous generation, while an optimized chip package fits add-in cards and other designs to optimize DIMM integration density.

• Leo 2 E-Series provides direct CPU-attached CXL 3.2 memory expansion via PCIe 6 x16 host connectivity. It delivers additional memory capacity without requiring another CPU socket and enables infrastructure providers to redeploy previously deployed memory in new, state-of-the-art cloud servers supporting high-volume workloads
• Leo 2 P-Series enables disaggregated CXL memory architectures with pooling and sharing across hosts, supported by dual-port PCIe 6 x8 connectivity and dynamic capacity management. Hosts can draw pooled memory on demand instead of over-provisioning every server, turning stranded DRAM into a rack-level resource increasing utilization which is critical in a memory supply constrained environment

A common foundation for reliable, interoperable memory deployment and re-use
Across the Leo family, hyperscale-grade RAS and memory-health management support reliable operation for evolving compute and memory platforms. Purpose-built memory test engines and automated repair engines help extend maximum lifetime for existing memory DIMMs, assist with pre-deployment testing, and identify reliable DIMMs for reuse. Enhanced memory error reporting, event recording, scrubbing, customizable thermal management, and resilient firmware updates help protect workloads and extend memory service life. Workload monitoring, performance profiling, hotness tracking, software-defined data placement, and latency optimization help fine-tune memory placement and access latency for long-context agentic AI and general purpose workloads. Telemetry and management integration, together with Astera Labs’ COSMOS software suite, provides fleet-wide visibility as operators combine previously deployed DDR4, newly deployed DDR5 in modern cloud server fleets, pooled, and accelerator-attached capacity across the rack.

“Agentic AI is where the economics of AI infrastructure are being decided, and those economics depend on putting every usable gigabyte of memory to work,” said Thad Omura, SVP, compute connectivity group, Astera Labs. “The enhanced Leo family gives infrastructure providers purpose-built ways to connect memory to accelerators, CPUs, and hosts across the rack – turning previously deployed and stranded capacity into a resource that new AI and cloud workloads can use. We’re seeing that translate into broader customer engagement across AI labs, hyperscalers, and neoclouds.”

The enhanced Leo family was developed by Astera Labs in close collaboration with CPU and GPU ecosystem partners, including AMD, Arm, Intel, and major memory suppliers, alongside additional hyperscale and OEM collaborators. The family is sampling today with hyperscaler customers.

Ecosystem Support
“Agentic AI is increasing demand for balanced systems that can move and process more data without sacrificing efficiency. AMD EPYC processors deliver leadership performance, exceptional memory bandwidth and capacity, and high-speed I/O across the broadly deployed x86 platform. Our collaboration with Astera Labs around CXL extends that foundation, giving customers greater flexibility to scale memory-intensive AI and cloud workloads and improve infrastructure utilization,” said Robert Hormuth, corporate VP, architecture and strategy, AMD.

“As AI infrastructure evolves, agentic AI, reinforcement learning and database workloads are driving demand for higher-capacity memory. Arm and Astera Labs are working together to pair Arm AGI CPU with Leo CXL Smart Memory Controllers, helping customers meet these growing requirements while maintaining scalable performance,” said Eddie Ramirez, VP, go-to-market, cloud AI, Arm.

“CXL was created to bring greater flexibility and efficiency to memory across the data center. Technologies like Astera Labs’ Leo Smart Memory Controllers help turn that vision into reality, demonstrating how ecosystem innovation can help customers get more out of their AI infrastructure and support the next generation of data-intensive workloads,” said Srini Krishna, fellow, data center group, Intel

“We are contributing to the evolution of AI infrastructure through the development of CXL memory solutions designed to help address the growing memory demands of modern data centers. We are excited to collaborate with Astera Labs to help ensure our DRAM solution offer strong interoperability within the evolving CXL ecosystem, and remain committed to supporting a scalable, high-performance memory architecture for the AI era,” said Jangseok Choi, VP, product planning team, Samsung Electronics.