Panmnesia Unveils Next-Stage CXL Switch and Controller

Panmnesia presented its next-stage CXL controller and a fabric switch built on it at ISCA 2026.ISCA (the International Symposium on Computer Architecture), a leading conference in the field, took place Raleigh, USA, from June 27 to July 1.

Unlike the common approach of attaching devices directly to the CPU without a switch, the controller-and-switch design Panmnesia is presenting connects more devices and expands memory capacity much further, while keeping latency in a similar range and improving total system bandwidth.

Background
As large-scale AI workloads such as AI agents and LLMs become common, so does the demand for memory capacity. This has raised interest in interconnects that let a CPU attach more memory flexibly—CXL chief among them.

The momentum reaches beyond academia. Companies building and deploying real CXL products and prototypes are now publishing results of their own. ISCA 2026 accepted two industry CXL papers—one from Meta and one from Panmnesia.

Technical Highlights
The paper describes Panmnesia’s next-stage CXL controller and the fabric switch built around it. The main contributions of each are summarized below.

1. Next-Stage CXL Controller: Lower Latency by Design
   The controller lowers latency through its design. Because CXL shares the same physical interface as PCIe, early CXL designs were commonly built by adapting existing PCIe IP—a practical way to reach silicon quickly. That path, however, carried over PCIe-oriented behavior that can add latency. The next-stage CXL controller reworks these parts to bring latency down.

   One concrete example is about layer-level synchronization overhead. Like PCIe controllers, early CXL designs typically kept a separate buffer at each layer and managed their timing independently, so moving data between internal layers carried a significant synchronization cost. Panmnesia’s controller instead shares buffers across layers, removing much of that overhead, and adds further per-layer optimizations to reduce latency more.

2. Fabric Switch: Better Connectivity Through Port-Based Routing
   The switch’s defining feature is support for Port-Based Routing (PBR), which forwards data using an identifier (port ID) assigned to each device. Hierarchy-Based Routing (HBR)—used in PCIe and early CXL—can connect devices only in a hierarchy, or tree. PBR removes that constraint, letting devices be wired into any topology. The resulting mesh of interconnections resembles woven cloth, which is where the term “fabric” comes from.

   The switch supports both PBR and HBR, so connections on the fabric can be arranged as the system requires and data paths optimized accordingly. Transfers can be scheduled flexibly, and performance stays stable even with many devices attached. Because the next-stage CXL controller is built in, latency stays low as well.

The net effect: compared with attaching a multi-headed device (MHD) directly to the CPU—the usual method for CXL memory expansion—Panmnesia’s fabric switch supports larger memory expansion while keeping latency in a similar range and improving total system bandwidth. With early CXL, only a handful of compute nodes could connect to a single CXL memory; Panmnesia’s switch scales to dozens of nodes or more, and the paper’s evaluation showed stable performance with as many as 64 nodes.

“There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached MHDs stayed the norm even though they were harder to scale. Our work shows this is not an inherent limit of CXL or CXL switches—it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together,” said Myoungsoo Jung, CEO, Panmnesia.

Meanwhile, Panmnesia has developed the technology further into the PCIe 6.4-CXL 3.2 Fusion Switch, now available as pre-release chips. The controller has gone a step further—adding the latest CXL 4.0 features—and is now available as the PCIe 7.0-CXL 4.0 Combo IP. Panmnesia will present the paper on June 29 (local time) in the Industry Session.

Availability
Panmnesia’s Partners can request pre-release chips and pilot systems for the PCIe 6.4-CXL 3.2 Fusion Switch, as well as the PCIe 7.0-CXL 4.0 Combo IP.