Panmnesia to Mass-Produce PCIe 6.4-CXL 3.2 Fusion Switch

Panmnesia, a South Korean fabless company developing link solutions for AI infrastructure, announced that it will mass-produce its PCIe 6.4-CXL 3.2 fusion switch chip in the second half of this year.

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The chip is the world’s only silicon to fully implement the CXL 3.2 specification, including Port-Based Routing (PBR). Panmnesia first unveiled a sample of the silicon in October last year.

Product Overview
This chip supports both PCIe and CXL protocols on a single die, enabling connectivity across a wide range of devices that make up modern data centers and HPC environments – including PCIe-based GPU, PCIe switches, CXL CPUs, CXL memory expanders and CXL-based AI accelerators.

In particular, Panmnesia’s PCIe 6.4-CXL 3.2 fusion switch enables composable architecture – a structure in which diverse system resources are pooled, managed independently, and flexibly allocated based on application demand – to be implemented at rack scale, minimizing resource waste across AI data centers and HPC environments. This translates into reduced CapEx and OpEx for systems handling large-scale workloads, including LLMs, RAG, deep learning recommendation models (DLRM), and MPI-based scientific simulations.

Key Differentiators
As demand for AI grows rapidly, enterprises are operating large numbers of accelerators in parallel to deliver more advanced services powered by large-scale AI models. In this environment, the overall performance of a system depends not only on the compute power of individual accelerators, but equally on how quickly and efficiently they can communicate with others. Panmnesia’s switch maximizes performance per dollar in AI data centers by accelerating this communication through the following differentiating capabilities.

World’s Only Port-Based Routing Support
Panmnesia’s switch supports both port-based routing (PBR) and hierarchy-based routing (HBR) on a single chip. Unlike HBR, which limits connectivity to a tree structure centered on the CPU, PBR allows switches and devices to be freely interconnected in any topology. This means data paths between devices can be flexibly designed, shortening data transfer routes and playing a critical role in improving system performance. Furthermore, Panmnesia’s switch chip enables Direct Peer-to-Peer communication on a fabric built with port-based routing, allowing devices to exchange data directly with minimal CPU involvement and maximizing communication efficiency. Panmnesia is currently the only company in the industry to offer a switch chip with port-based routing support
Large-Scale Fabric via Switch Cascading
With cascading support, multiple switches can be chained together to unify thousands of devices across multiple server racks into a single fabric – without relying on high-latency networks such as Ethernet
Accelerated Device-to-Device Communication
The switch supports all CXL sub-protocols – CXL.cache, CXL.mem, and CXL.io – ensuring cache coherency between devices and minimizing unnecessary data copies. It also fully supports PCIe Gen 6 data transfer speeds of 64GT/s, further enhancing large-scale data movement performance
Proprietary Ultra-Low-Latency Controller
Panmnesia’s switch chip is built on a fully proprietary controller and IP, another key differentiator. Designed and optimized for CXL architectures, the controller achieves double-digit nanosecond (ns) latency, boosting response time and throughput across the switch and overall system. The controller logic can also be freely modified to accommodate customer-specific requirements, enabling expansion into tailored custom solutions

Availability
Panmnesia’s PCIe 6.4-CXL 3.2 fusion switch silicon is out now and early access partners can request samples and pilot systems.