R&D: Five Articles on Non-Volatile Memory Technologies and Applications

R&D: From In-Place Updates to Out-of-Place Selections, Reconsidering Write Disturbance in Non-Volatile Memory
Authors present LearnWD, an approach that mitigates the WD problem in NVM via coupling machine learning with out-of-place updates.

ACM Transactions on Storage has published an article written by  Shuyue Zhou, Ronglong Wu, Hao Li, Zhenggang Lin, School of Informatics, Xiamen University, Xiamen, China, Chengshuo Zheng, Xiamen University, Xiamen, China, Zhirong Shen, Yijie Zhong, Fulin Nan, Yiming Zhang, School of Informatics, Xiamen University, Xiamen, China, and Jiwu Shu, Xiamen University, Xiamen, China and Tsinghua University, Beijing, China.

Abstract: “Non-volatile memory (NVM) opens up new opportunities to resolve scaling restrictions of main memory, yet it is still hindered by the write disturbance (WD) problem. The WD problem mistakenly transforms the values of NVM cells, hence seriously deteriorating memory reliability and downgrading access performance. Existing studies mainly mitigate the WD problem via encoding WD-prone data patterns under in-place updates, yet we find that when turning to out-of-place updates, they can gain the potential to reduce more WD errors. We present LearnWD, an approach that mitigates the WD problem in NVM via coupling machine learning with out-of-place updates. LearnWD first employs clustering algorithms to classify the stale data based on the error proneness. To perform a write operation, LearnWD carefully examines the aggressivity of new data and the error proneness of stale data, so as to speculatively minimize the resulting WD errors. We conduct extensive experiments using 15 real-world datasets with different data types, showing that LearnWD can assist a variety of data encoding schemes to further reduce 19.5% of WD errors, shorten 10.1% of write latency, and extend 22.2% of write endurance.“

R&D: Zero2M, Optimizing Tenant-Level I/O Management for Future Faster NVMe Storage with FPGA
Paper presents Zero2M, a novel CPU-free system designed to optimize the additional CPU costs and latency overhead in tenant-level I/O management for future faster NVMe SSDs.

ACM Transactions on Reconfigurabl Technology and Systems has published an article written by Wenjie Wang, Bo Peng, Jianguo Yao, and Haibing Guan, Shanghai Jiao Tong University, China.

Abstract: “High-speed non-volatile memory express (NVMe) solid-state drives (SSDs) are shared by multiple tenants in cloud scenarios to improve resource utilization. Tenant-level I/O management is necessary to achieve reliable QoS control during sharing. Unfortunately, our investigation finds that CPUs inevitably participate in I/O management for existing solutions because SSDs are not tenant-sensitive and have limited internal computing resources. It introduces additional CPU costs and latency overhead when serving future faster SSDs. We propose that the Field Programmable Logic Gate Array (FPGA) is a promising alternative for freeing tenant-level I/O management from CPUs. However, implementing tenant-level I/O management using the FPGA requires addressing the following challenges: (1) System compatibility and tenant identification. (2) Efficient FPGA workflows that will not become a bottleneck. (3) Fast I/O management workflow that introduces the lowest additional CPU costs and latency.“

“This paper presents Zero2M, a novel CPU-free system designed to optimize the additional CPU costs and latency overhead in tenant-level I/O management for future faster NVMe SSDs. Zero2M proposes a dedicated FPGA-based NVMe controller to preserve system compatibility and identify tenants using the namespace mechanism in NVMe. It allows I/O management without modifying host software, which existing solutions cannot achieve. The parallelized and pipelined workflows are proposed in the controller to accelerate I/O command processing and prevent the controller from becoming a bottleneck for the I/O management workflow. The read/write speed of the Zero2M controller is 4.65\(\times\)/4.92\(\times\) faster than the state-of-the-art hardware-accelerated controller. The I/O management workflow is formulated as a novel parallelized and pipelined accelerator and integrated into the workflow of Zero2M’s controller. It optimizes additional CPU costs and latency overhead for tenant-level I/O management. Experiments present that Zero2M reduces an average of 3.01\(\times\) CPU usage while maintaining the lowest latency overhead (7.62\(\times\) lower on average) compared to the state-of-the-art solution. It also removes the CPU dependency for tenant-level I/O management for the first time.“

R&D: K-ion intercalation memristors in prussian blue analogs revealed by C-AFM for Non-Volatile memory and Neuromorphic Computing
Work provides the first demonstration of intercalation-driven resistive switching under ultrafast voltage sweeps, with PW operating up to 200 V/s and PB up to 50 V/s; This unprecedented speed establishes PBAs as a distinct, high-rate class of K-ion intercalation memristors suitable for fast, high-density neuromorphic and memory applications.

arXiv has published an article written by L. B. Avila, O. Leuve, Institute of Condensed Matter and Nanosciences (IMCN),Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, M. Pohlitz, Faculty of Physical Engineering/Computer Sciences, University of Applied Sciences Zwickau, 08056 Zwickau, Germany, M. A Villena, Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, Facultad de Ciencias, Avd. Fuentenueva s/n, 18071 Granada, Spain, Ramón Torres-Cavalillas, Instituto de Ciencia Molecular, Universitat de Valencia, Valencia, 46980 Spain, C. Ducarme, A. Lopes Temporao, T. G. Coppée, A. Moureaux, S. Arib, nstitute of Condensed Matter and Nanosciences (IMCN),Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, Eugenio Coronado,Instituto de Ciencia Molecular, Universitat de Valencia, Valencia, 46980 Spain, C. K. Müller,Faculty of Physical Engineering/Computer Sciences, University of Applied Sciences Zwickau, 08056 Zwickau, Germany, J. B. Roldán,Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, Facultad de Ciencias, Avd. Fuentenueva s/n, 18071 Granada, Spain, B. Hackens, and F. Abreu Araujo, Institute of Condensed Matter and Nanosciences (IMCN),Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium.

Abstract: “Here, we demonstrate K-ion intercalation-mediated resistive switching in Prussian blue analogs (PBAs), a mechanism widely exploited in potassium batteries but not previously resolved at the nanoscale for memristive operation. Using C-AFM, we directly visualize and electrically control this intercalation process within sub-100-nm volumes, revealing reversible, localized conductance modulation driven by K-ion intercalation and Fe2+/Fe3+ redox reconfiguration. This nanoscale operability highlights the exceptional potential of PBAs for high-scalable and low-dimension memristor-based devices integration. Due to their modular composition, PBAs constitute a chemically rich, earth-abundant materials platform whose electronic and ionic properties can be precisely tuned for specific device functions. K-ion intercalation PBA-based memristor devices, with their singlestep, aqueous, and room-temperature fabrication, enable low-cost, large-scale processing compatible with CMOS, without any additional post-fabrication processing. Our findings establish PBAs as a new class of intercalation memristors with scalable nanoscale switching and exceptional materials versatility, toward highly integrated neuromorphic and non-volatile memory technologies. This work provides the first demonstration of intercalation-driven resistive switching under ultrafast voltage sweeps, with PW operating up to 200 V/s and PB up to 50 V/s. This unprecedented speed establishes PBAs as a distinct, high-rate class of K-ion intercalation memristors suitable for fast, high-density neuromorphic and memory applications.“

R&D: Triphasic BiFeO₃–BaTiO₃–CoFe₂O₄ nanocomposite architectures elucidating efficient magnetoelectric coupling and low–leakage non–volatile memory storage
Persistent magnetoelectric investigation of single–phase multiferroic BiFeO₃ at room temperature continues to draw significant attention due to its potential in multifunctional device applications, particularly in logic–based memory storage systems.

Materials Science in Semiconductor Processing has published an article written by Izhar Sagheer, Muhammad Luqman, Muhammad Umar Salman, Centre of Excellence in Solid State Physics, University of the Punjab, Lahore, 54590, Pakistan, Shahid M. Ramay, Physics and Astronomy Department, Faculty of Science, King Saud University (KSU), Riyadh, Saudi Arabia, Zaffar Iqbal, Department of Materials Science and Engineering, University of Houston, Texas, USA, and Shahid Atiq, Centre of Excellence in Solid State Physics, University of the Punjab, Lahore, 54590, Pakistan.

Abstract: “The persistent magnetoelectric investigation of single–phase multiferroic BiFeO₃ at room temperature continues to draw significant attention due to its potential in multifunctional device applications, particularly in logic–based memory storage systems. In this study, a series of triphasic nanocomposites with the nominal composition (1-x-y)BiFeO₃+xBaTiO₃+yCoFe₂O₄ with varying x and y were synthesized via a combined solution–gelation auto–ignition and mechanical grinding route. Structural analysis through X–ray diffraction analysis confirmed the formation of pure crystalline phases, while the field emission scanning electron microscopy revealed a granular and porous morphology with irregular particle distribution. Among all the compositions, the sample with (x, y) = (0.08, 0.12) demonstrated a moderate response to the applied electric field and delivered the highest polarization of ∼0.0015 μC/cm² and an energy conversion efficiency of 70 % attributed to electric domains. The composition also exhibited a minimal reversal time of ∼0.16 ms, characterized by minimal leakage current and exhibited highest spontaneous magnetization ∼9.35 emu/g. Furthermore, the magnetoelectric coupling and stable write–read–erase–rewrite performance highlight the suitability of these nanocomposites for advanced non–volatile multistate memory storage devices.“

R&D: AKV, Agile Read-Efficiently Key-Value OLTP Engine for Non-Volatile Memory
Authors introduce AKV (Agile Key-Value), an NVM-only OLTP storage engine designed to provide effective space utilization, high throughput, and fast failure recovery.

IEEE Transactions on Knowledge and Data Engineering has published an article written by Jianbin Qin, Shuai Liu, SICS, Shenzhen University, Shenzhen, China, Tianyu Wang, Shenzhen University, Shenzhen, China, Yuxing Chen, Anqun Pan, Tencent Inc., Shenzhen, China, Rui Mao, SICS, Shenzhen University, Shenzhen, China, Yuxuan Qiu

Beijing Institute of Technology, Zhuhai, China, Makoto Onizuka, Osaka University, Osaka, Japan, and Chuan Xiao, Osaka University, Osaka, Japan, and Nagoya University, Nagoya, Japan.

Abstract: “Non-volatile memory (NVM), as an emerging storage technology, offers several advantageous features for OLTP engines, including byte-addressability, high capacity, low energy consumption, and data persistence across power failures. Despite these benefits, the current mainstream OLTP engines still commonly adopt a hybrid architecture that deeply couples DRAM with NVM, which results in a complex system architecture and high recovery costs. In this paper, we aim to construct a highly available, stable, and recoverable OLTP engine that guarantees ACID properties through an agile system architecture. We introduce AKV (Agile Key-Value), an NVM-only OLTP storage engine designed to provide effective space utilization, high throughput, and fast failure recovery. AKV addresses the challenges of NVM space management, write redundancy, and concurrency control with two novel techniques: dual-version concurrency control and circular dual-version storage. Experimental results demonstrate that AKV achieves higher throughput (up to 69.7%) and faster recovery (up to 54×) compared to existing storage engines in most scenarios of the TPC-C benchmarks. Additionally, the codebase of AKV (4k+ lines) is more concise than that of SOTA OLTP engines like Zen (8k+ lines) and Falcon (11k+ lines). In addition, this study innovatively proposes a read abort optimization strategy based on dynamic version changes. The experimental results show that this strategy can significantly reduce the transaction abort rate of AKV in specific workload scenarios while maintaining stable system throughput, achieving a maximum reduction of up to 73% in the abort count.“