SK Hynix NAND Product Solutions Assigned Thirteen Patents

UART communication of telemetry and debugging data using optical signals
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12475013) developed by Ham; Hoeun, Folsom, CA, for “UART communication of telemetry and debugging data using optical signals.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to communicating telemetry and debugging data of a memory system using optical signals. An enclosed memory device has an optical indicator and receives a data request. In response to the data request, the enclosed memory device obtains internal activity data stored in the memory device, encodes the internal activity data into an electrical signal, and drives the optical indicator with the electrical signal to generate a visible light signal carrying the internal activity data. In some embodiments, the enclosed memory device includes a solid-state drive. In some embodiments, the internal activity data includes telemetry data stored by the enclosed memory device while the memory device is processing a sequence of memory access requests including at least one of a read request and a write request.”

The patent application was filed on 2023-06-30 (18/217347).

Automatic selection of computational NVM targets
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12468461) developed by Trika; Sanjeev, Portland, OR, for an “automatic selection of computational non-volatile memory targets.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods may provide for memory controller technology that detects an application function, a data specifier associated with the application function, and one or more operating parameters associated with the application function, generates execution estimates for a plurality of computational storage devices based on the application function, the data specifier, the operating parameter(s), and one or more device capabilities associated with the plurality of computational storage devices, and selects a target storage device from the plurality of storage devices based on the execution estimates.”

The patent application was filed on 2021-08-27 (17/459414).

Root complex integrated endpoint emulation of discreet PCIE endpoint
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12455850) developed by Ooi; Eng Hun, Georgetown, Malaysia, Lim; Su Wei, Penang, Malaysia, Tan; Kuan Hua, Coquitlam, CA, and Kalluraya; Prashanth, Sunnyvale, CA, for a “root complex integrated endpoint emulation of a discreet PCIE endpoint.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.”

The patent application was filed on 2017-09-28 (15/718110).

Managing quality of service by allocating die parallelism with variable queue depth
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12457175) developed by Bahirat; Shirish, Longmont, CO, Ramalingam; Anand, Portland, OR, Albert Jayaraj; Solomon Sagar, Gainesville, FL, Sachin; Fnu, Blacksburg, VA, and Guo; Xin, San Jose, CA, for “managing quality of service by allocating die parallelism with variable queue depth.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.”

The patent application was filed on 2021-06-23 (17/355915).

Device, system and method for memory repair with multi-cell switching
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12451212) developed by Radhakrishnan; Aravinda, Sunnyvale, CA, Cheung; Marcus Wing-Kin, Cupertino, CA, Somasekhar; Dinesh, Portland, OR, Bhandaru; Naga Mallika, Fremont, CA, Nelms; Michael, Fort Collins, CO, Gonzalez Gutierrez; Rodrigo, and Chen; Kaitlyn, Hillsboro, OR, for “device, system and method for memory repair with multi-cell switching.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Techniques and mechanisms for a memory device to support memory repair functionality for a column of a memory array. In an embodiment, the column comprises first memory cells and second memory cells, where switch circuitry is coupled between multiple signal lines and the column. Control circuitry transitions the switch circuitry to a state which corresponds to a defective one of the first cells. The state switchedly decouples the defective cell, and an adjoining one of the first cells, each from respective ones of the signal lines. During the state, two or more of the signal lines are able to communicate each to a different respective one of the second cells. In another embodiment, the switch circuitry is transitioned to the state based on an identifier of the defective cell, and independent of whether any other cell of the column has been identified as defective.”

The patent application was filed on 2020-06-25 (16/912498).

Workload scheduler for memory allocation
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12443443) developed by Wang; Yipeng, Wang; Ren, Tai; Tsung-Yuan C., Portland, OR, Yuan; Yifan, Champaign, IL, Pathak; Pravin, Bridgewater, NJ, Vedantham; Sundar, Allentown, PA, and MacNamara; Chris, Limerick, Ireland, for a “workload scheduler for memory allocation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.”

The patent application was filed on 2020-02-24 (16/799745).

Loading frame for high I/O count packaged semiconductor chip
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12444664) developed by Smalley; Jeffory L., Olympia, WA, Prabhugoud; Mohanraj, Hillsboro, OR, Klein; Steven A., Chandler, AZ, and Liu; Mengqi, Hillsboro, OR, for a “loading frame for high I/O count packaged semiconductor chip.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus is described. The apparatus includes a loading frame for mounting a packaged semiconductor chip and a heat sink for the packaged semiconductor chip to a socket. The loading frame is comprised of metal. The loading frame has at least one frame leg where the metal is folded to re-enforce a strength of the frame leg.”

The patent application was filed on 2020-12-23 (17/132391).

Devices and methods for managing command fetch and command execution
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12430133) developed by Patel; Dimpesh, Surrey, CA, Hughes; Jonathan, Longmont, CO, Greer; Teddy, Grayson, KY, Vemula; Neelesh, Santa Clara, CA, and de Vries; Jonathan, Folsom, CA, for “devices and methods for managing command fetch and command execution.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device and related method, the device including system memory for storing at least two queue groups, each of which includes commands, and processing circuitry. For each respective queue group, the processing circuitry determines an allocated command value indicative of a number of commands that are capable of being fetched from the respective queue group, determines a number of outstanding commands to be fetched from the respective queue group, and compares the allocated command value to the number of outstanding commands to be fetched for the respective queue group. When the allocated command value is greater than the number of outstanding commands to be fetched for the respective queue group, the processing circuitry designates the respective queue group as an available queue group. The processing circuitry then selects a queue group from the designated available queue groups and fetches at least one command from the selected queue group.”

The patent application was filed on 2024-05-09 (18/659834).

Variable node data management for integrity check in memory systems
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12423176) developed by Kwok; Zion, Burnaby, Canada, for a “variable node data management for integrity check in memory systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a variable node that corresponds to a first data bit in a block of data, and obtains check node data from each check node. A hard decision likelihood is determined based on a check node data set including the check node data of each of the set of check nodes. The electronic device dynamically determines an adjustment factor based on the hard decision likelihood. Variable node data is determined for each of the set of check nodes based on the adjustment factor. In some embodiments, each check node is configured to verify validity of a set of data bits including the first data bit, and the check node data of each of the set of check nodes indicates a likelihood of the set of data bits being erroneous.”

The patent application was filed on 2023-07-19 (18/224030).

Dynamic power management among multiple memory devices
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12422914) developed by Reimers; Niels, Meadow Vista, CA, and Morning-Smith; Andrew, Vancouver, Canada, for a “dynamic power management among multiple memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to dynamic power management among multiple memory devices of an electronic system. A plurality of memory devices are coupled into a ring of memory devices, and passes a power data packet along a power control path that tracks the ring of memory devices continuously. During a current cycle, a first memory device receives the power data packet from an upstream memory device on the power control path, and the power data packet includes at least a system power level indicating total power consumption of the plurality of memory devices. The first memory device sets a current power level of the first memory device based on the received power data packet, updates the power data packet based on the current power level, and sends the updated power data packet to a downstream memory device on the power control path.”

The patent application was filed on 2023-09-29 (18/375362).

Host bandwidth optimized data stream memory writes
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12411773) developed by Natarajan; Shankar, Natarajan; Sriram, Folsom, CA, and Kowalczyk; Grzegorz, Gdynia, Poland, for a “host bandwidth optimized data stream memory writes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and related method, including memory and processing circuitry, which is to write data of a data stream. The memory includes a first memory portion of a first density and a second memory portion of a second density. The processing circuitry receives a write request. The processing circuitry is then to select to write the data to the first memory portion based on a characteristic of the data stream, wherein both the first memory portion and the second memory portion are available to be written to, and the processing circuitry then causes the data to be written to the first memory portion. The processing circuitry may select to write the data to the first memory portion based on a size of the data stream and/or based on a bandwidth of writing data of the data stream to the memory.”

The patent application was filed on 2023-05-25 (18/201943).

Dynamic single-level cell write through in memory devices
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12386745) developed by Kalwitz; George, Mead, CO, for a “dynamic single-level cell write through in memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.”

The patent application was filed on 2023-11-10 (18/388782).

On-SSD-copy techniques using copy-on-write
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA, has been assigned a patent (12366986) developed by Li; Peng, Beaverton, OR, Trika; Sanjeev N., and Estrada; David C., Portland, OR, for “on-SSD-copy techniques using copy-on-write.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA’s entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.”

The patent application was filed on 2021-03-16 (17/203174).