R&D: Five Articles on Memories Technologies and Developments

R&D: Harnessing Page Access Frequency Distribution for Efficient Memory Tiering
Authors present Memtis, a tiered memory system that adopts informed decision-making for page placement and page size determination.

ACM Transactions on Computer Systems has published an article written by Taehyung Lee, Sungkyunkwan University – Natural Sciences Campus, Suwon-si, Korea (the Republic of), Sumit Monga, Virginia Tech, Blacksburg, USA, Young Ik Eom, Sungkyunkwan University – Suwon Campus, Suwon, Korea (the Republic of), and Changwoo Min, Igalia, A Coruña, Spain.

Abstract: “Advances in memory technologies (e.g., HBM, DRAM, NVM) and interconnects (e.g., CXL) have significantly enhanced the flexibility of utilizing memory resources in modern computer systems. As this trend continues, memory resources are poised to become fully composable in the near future. This increasing flexibility also accelerates the demand for effective tiered memory systems capable of performing well across diverse scenarios and workloads. However, the effectiveness of existing tiered memory systems heavily depends on system configuration (e.g., the ratio of fast tier to capacity tier), memory access patterns, and page sizes (base vs. huge). Their reliance on simple heuristics and static thresholds for detecting page hotness, and limited consideration of page sizes, results in suboptimal (often pathological) page placement decisions. To build a robust and effective system, tiered memory management must holistically account for overall memory access patterns in conjunction with the tiering environment.“

“We present Memtis, a tiered memory system that adopts informed decision-making for page placement and page size determination. Memtis leverages access distribution of allocated pages to optimally approximate the hot data set to the fast tier capacity. Moreover, Memtis dynamically determines the page size that allows applications to use huge pages while avoiding their drawbacks by detecting inefficient use of fast tier memory and splintering them if necessary. To further enhance its practicality across diverse scenarios, Memtis effectively supports the dynamic allocation of fast tier memory if there is a specific performance requirement, such as a target hit ratio. Our evaluation shows that Memtis outperforms existing tiered memory systems under various workloads and tiering configurations by up to 169.0%, showing its robustness.“

R&D: 10T2R Non-volatile SRAM Cell design with High-reliability
In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed.

Solid-State Electronics has published an article written by So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, and Ga-Won Lee, Chungnam National University, South Korea.

Abstract: “In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.“

R&D: Temperature-dependent Analysis of Retention and Write Characteristics of STT-MRAM Cells
Authors investigated Δ over a range of − 25 ° C– 150 ° C⁠, and I C from − 25 ° C to 25 ° C across devices with four different storage layer (SL) thicknesses.

Journal of Applied Physics has published an article written by Shanmukha Mangadahalli Siddaramu, Meike Hindenberg, Fraunhofer Institute for Photonic Microsystems, 01109 Dresden, Germany, Johannes Müller, GlobalFoundries Fab1 LLC and Company KG, 01109 Dresden, Germany, Maik Wagner-Reetz, and Jyotirmoy Chatterjee, Fraunhofer Institute for Photonic Microsystems, 01109 Dresden, Germany.

Abstract: “Spin-transfer torque magnetic random-access memory (STT-MRAM) is being investigated for automotive applications. However, to ensure reliable operation across the wide temperature ranges required in automotive systems, it is important to understand the thermal variation of data retention and switching characteristics, such as thermal stability factor (⁠ Δ⁠), critical switching current (⁠ I C⁠), and STT efficiency. We investigated Δ over a range of − 25 ° C– 150 ° C⁠, and I C from − 25 ° C to 25 ° C across devices with four different storage layer (SL) thicknesses. The Δ values were extracted using the macrospin (MS) and the domain wall nucleation and propagation (DW) models. Both models well explain the decreasing trend of Δ as a function of temperature. Δ decreases by 60%–70% and 63%–65%, respectively, for MS and DW model when the temperature is increased from − 25 to 150 ° C⁠. It is also observed that at higher temperatures, Δ converges for all SL thicknesses to a similar value, indicating stronger thermal sensitivity for thicker layers. As a result, the blocking temperature is larger for thicker SL. The Gilbert damping constant (⁠ α⁠), domain wall width (⁠ δ w⁠), and domain wall energy density (⁠ σ w⁠) of the devices were also extracted using the DW model. The rapid reduction in σ w with temperature suggests a transition in magnetization reversal mechanism from the DW model to multi-domain nucleation and propagation at higher temperatures. This indicates that the magnetization reversal process is highly dependent on operating thermal conditions. I C and STT-switching efficiency decrease with increasing temperature, predominantly due to the reduction in Δ⁠. In addition, I C also reduces upon increasing the SL thickness, which is attributed to a decrease in α⁠. The practical switching efficiency (⁠ κ⁠) is also analyzed, which is crucial for benchmarking STT-MRAM performance under application-specific thermal conditions.“

R&D: Architecture of 3D Magnetic Domain Wall Memory for Suppressing Bit-shift Error
Authors propose an architecture for the suppression of magnetic domain wall shift error in 3D magnetic domain wall memory.

Journal of Applied Physics has published an article written by Pham Nam Hai, Department of Electrical and Electronic Engineering, Institute of Science Tokyo, 2-12-1 Ookayama, Meguro, Tokyo 152-0033, Japan, Takanori Shirokura, Institute of Innovative Research, Institute of Science Tokyo, 4259 Nagatsuta-cho, Midori-ku, Yokohama, Kanagawa 226-8503, Japan, and Nguyen Huynh Duy Khang, Department of Physics, Ho Chi Minh City University of Education, 280 An Duong Vuong Street, District 5, Ho Chi Minh City 738242, Vietnam.

Abstract: “We propose an architecture for the suppression of magnetic domain wall shift error in 3D magnetic domain wall memory, which utilizes the spatially modulated perpendicular magnetic anisotropy (PMA) of magnetic layers that are deposited on the side walls of multilayers of different oxide materials. We experimentally identified the oxide material candidates for such implementation and found that CrO_x can generate the largest PMA while GdO_x generates the smallest PMA of Pt/Co/Pt multilayers. Our proposed architecture can be a key to realizing 3D magnetic domain wall racetrack memory with low bit-shift error.“

R&D: Novel Computing-in-memory Array based on STT-MRAM using High on–off Ratio 2T-1M Bit-cell
Paper introduces an innovative computing-in-memory array and its application in edge AI inference based on spin-transfer-torque magnetoresistance random access memory.

AIP Advances has published an article written by Wenbiao Zhang, Xiang Feng, Yinuo Shi, Bo Liu, and Peng Liu, State Key Laboratory of Spintronics Devices and Technologies, Hangzhou, Zhejiang 311305, China.

Abstract: “With the rapid advancement of artificial intelligence (AI) and the explosion of data, there is an increasingly urgent demand for computing-in-memory technology. This paper introduces an innovative computing-in-memory array and its application in edge AI inference based on spin-transfer-torque magnetoresistance random access memory. The bit-cell of this array is composed of two transistors and one magnetic tunnel junction (2T-1M), which greatly improves the on/off ratio to 50 at a sampling frequency of 23 MHz, which is 25 times larger than a conventional cell. Correspondingly, the current rate of change is employed instead of the current magnitude in a conventional array. We also explore the non-idealities, including sampling frequency and resistance variation, which indicates that the proposed array maintains better stability. The array performs image classification using the MNIST dataset and achieves an accuracy of 96.3%, which is approximately equivalent to the accuracy of software. Finally, the 2T-1M array achieves a 48.8% lower energy consumption compared to the conventional 1T-1M array at a size of 64 (rows) × 64 (columns).“

R&D: Swap on Sky, Skyrmion-Based In-Memory Swapping Architecture to Break Memory Wall
Paper enables an optimized SKRM-based in-memory swapping mechanism, which not only realizes in-memory swapping to break the memory wall but also jointly considers the costs associated with skyrmion creation and shifting, further enhancing performance and energy efficiency.

ACM Transactions on Architecture and Code Optimization has published an article written by Sin Chen, YiKai Huang, Yao-Yu Liao, and Tseng-Y Chen, Department of Computer Science and Information Engineering, National Central University, Zhongli District, Taiwan.

Abstract: “Swapping operations, fundamental to algorithms in sorting, searching, graph processing, and machine learning, incur substantial data movement overhead between the CPU and host main memory due to the memory wall. Traditionally, swapping necessitates loading two elements from memory into CPU registers, performing the swap, and writing these elements back to their memory locations. This cycle of data transfer introduces significant latency caused by memory access delays and data movement overhead. To overcome this challenge, Computing-in-Memory (CiM) technologies have been proposed, enabling direct data manipulation within memory to eliminate costly CPU-memory transfers. Skyrmion Racetrack Memory (SKRM), an innovative non-volatile memory technology, is particularly suitable for implementing in-memory swapping due to its unique operational advantages. Unlike conventional DRAM, SKRM stores data as movable magnetic domains (skyrmions) along nanotracks, allowing data positions to be shifted efficiently through current pulses without physically transferring data outside memory. This inherent characteristic substantially reduces energy consumption and latency compared to DRAM, which demands explicit read and write operations for swapping. This paper enables an optimized SKRM-based in-memory swapping mechanism, which not only realizes in-memory swapping to break the memory wall but also jointly considers the costs associated with skyrmion creation and shifting, further enhancing performance and energy efficiency. To demonstrate the effectiveness of our solution, we integrate it into a decision tree-based machine learning framework, emphasizing the frequent swapping operations essential in decision tree construction. Experimental evaluations demonstrate promising results, highlighting significant reductions in both energy consumption and memory access latency.“