R&D : Three Articles on SSDs Technologies and Solutions

R&D: Unlocking Full Potential of Dual-Interface SSDs, Comprehensive Hardware and Software Perspective
Authors demonstrate the ability of Dual-Interface SSDs to reduce write amplification in traditional Copy-on-Write B-Tree data store.

ACM Transactions on Embedded Computing Systems has published an article written by Lok Yin Chow, The Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, Hong Kong, Yingjia Wang, The Chinese University of Hong Kong, Hong Kong, Hong Kong, Yuhong Liang, Great Bay University, Dongguan, China, and Ming-Chang Yang, The Chinese University of Hong Kong, Hong Kong, Hong Kong.

Abstract: “The legacy block interface for I/O benefits from data locality but faces challenges with I/O amplification due to the frequent small read-write operations common in most applications. Dual-Interface SSDs, which integrate block-interface Flash memory with byte-addressable memory, create opportunities for application redesign by reducing unnecessary read-write amplification on storage devices. However, current Dual-Interface SSD hardware remains limited in terms of size and functionality. Existing software designs for Dual-Interface SSDs often use the byte-addressable space as sequential logs with basic batch reclamation. While this space allows random access, and batch reclamation introduces significant tail latency caused by excessive read and write-back operations. To fully exploit the potential of Dual-Interface SSDs, we have developed a prototype on a hardware-software configurable platform. This publicly accessible Dual-Interface SSD offers realistic and optimized performance, overcoming the size and functionality limitations of previous designs. In addition, we demonstrate the ability of Dual-Interface SSDs to reduce write amplification in a traditional Copy-on-Write B-Tree data store. By employing two key techniques—Tree Pointer Relocation, which decouples indirection from the tree structure, and Tree Node Accommodation, which enables small-sized key-value pair updates to be processed directly in the byte-addressable space—we significantly improve the efficiency of storage operations. Our evaluation reveals that these techniques, when applied to Dual-Interface SSDs, achieve performance gains of 30.5% and 52.5% compared to a CoW B-Tree operating on traditional block-interface SSDs.“

R&D: Reliability, Security and Sustainability Challenges in 3D NAND Flash SSDs
Article explores the reliability, security, and sustainability of future 3D NAND flash SSDs.

IEEE Design & Test has published an article written by Biswajit Ray, Colorado State University, USA, Shyam Raghunathan, Micron Technology, USA, and Sudeep Pasricha, Colorado State University, USA.

Abstract: “This article explores the reliability, security, and sustainability of future 3D NAND flash SSDs. We discuss scaling challenges, their impact on reliability and radiation-induced vulnerabilities, along with potential countermeasures. Security concerns, including data sanitization and supply chain risks, are also discussed. Finally, we highlight sustainability issues related to storage carbon footprints. Our article emphasizes the need for innovative solutions to improve the resilience, security, and environmental impact of 3D NAND technology.“

R&D: Local Feedback and Dynamic Adjustment Best offset Prefetcher in CXL-SSD
Authors compare it with different prefetching algorithms and demonstrate that this method significantly reduces access latency.

Cluster Computing has published an article written by Shibao Li, Zhou Yang, Chengzhi Wang, Yunwu Zhang, Wei Dou, Xuerong Cui, and Jianhang Liu, College of Computer Science and Technology, China University of Petroleum (East China), Qingdao, 266580, Shandong Province, China

Abstract: “The imbalance between computing power and memory development in computing systems has given rise to the memory wall problem, which has become a significant bottleneck in the rapid advancement of AI and HPC. As a memory expansion solution, CXL-SSD significantly alleviates this issue. Prefetching technology predicts and preloads the data to be used, further mitigating the impact of long access latencies. However, the prefetching algorithm in the existing CXL-SSD is unable to flexibly adjust the prefetching strategy according to the workload characteristics, which affects the efficiency of the data access and the system performance. To this end, we designed a prefetching optimization scheme called LDBO based on local feedback and dynamic adjustment of the prefetch amount. LDBO evaluates local metrics to assess prefetching effectiveness and adjusts the Best-Offset prefetch amount accordingly to enhance performance. We compare it with different prefetching algorithms and demonstrate that this method significantly reduces access latency.“