R&D: Efficient Encoding Algorithm and Architecture for 2D Quasicyclic LDPC Codes with Applications to 2D Magnetic Recording

IEEE Transactions on Magnetics has published an article written by Karthik Bharadwaj, and Shayan Srinivasa Garani, Department of Electronic Systems Engineering, Indian Institute of Science, Bengaluru, India.

Abstract: “We propose an efficient encoding algorithm and architecture for two-dimensional (2-D) quasi-cyclic (QC) low-density parity-check (LDPC) codes. The encoding algorithm is derived based on the null space of the parity-check tensor obtained by tiling random permutation tensors satisfying certain girth constraints towards improved error correction performance. Our contributions are threefold: (a) First, the construction of 2-D LDPC codes is generalized to accommodate random tilings of permutation tensors, providing code design flexibility over prior work based on predefined shifts. We provide the conditions for obtaining girth greater than four and six, useful for deriving the parity-check tensor of the code algorithmically. (b) Based on the parity-check tensor, the generator tensor of the 2-D code is derived. We prove that the generator tensor of a 2-D code whose parity-check tensor has the same i-shifts within each block row, regardless of the j-shifts, comprises tiles of circulant tensors, useful for hardware realization. (c) Three different hardware architectures that trade-off hardware resources with speed and throughput are proposed. Finally, we analyze the performance of the code via simulations. The proposed 2-D codes are capable of correcting random errors and cluster errors by design. Specifically, for a 2-D LDPC code of rate 0.5 and size 50 × 100, the proposed approach with random shifts along with layered decoding achieves a 0.7 dB signal-to-noise ratio (SNR) gain for random errors at a code failure rate (CFR) of 10⁻⁵, and a 1.8 dB SNR gain for burst errors, compared to non-layered decoding with predefined shifts.“