R&D: Three Articles on Flash Memory

R&D: Fbrot, Implementing Flash Memory Based Root of Trust for Iot Terminals

Evaluation of the FBRoT prototype system shows that FBRoT incurs reasonable overhead, making it a practical security solution for resource-constrained IoT terminals.

SSRN has published an article written by Haotian Shi, State Key Laboratory of Cyberspace Security Defense, Institute of Information Engineering, and School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China, Siyuan Ma, Yuewu Wang, School of Cryptography, University of Chinese Academy of Sciences, Beijing 100049, China, Lingguang Lei, Xiamen University of Technology,Xiamen 361024, China, Shijie Jia, Xiamen University of Technology,Xiamen 361024, China, and Jiwu Jing, School of Cryptography, University of Chinese Academy of Sciences, Beijing 100049, China.

Abstract: “With the popularity of IoT applications, their security has become a focus of academic and industrial attention. Root of trust (RoT) may ensure that only the correct image can be loaded onto the platform of IoT terminal to protect the control flow integrity of the IoT terminal, and plays an important role in IoT terminal security. Existing RoT solutions for the IoT terminals require the introduction of additional hardware or modifications to existing hardware architectures. This does not meet the stringent size, cost, and power requirements of IoT terminal. In addition, some IoT terminals may be used for leasing, which requires their RoT to be able to be updated by the tenant. Existing RoT does not address the issue well. Therefore, this paper proposes an approach to build a RoT for IoT terminals using flash memory, named FBRoT. FBRoT implements the RoT security functions based on the computing power of NAND flash FTL (Flash translation layer). NAND flash is a versatile component for IoT terminals and usually used to store system image. Flash read and write operations for image loading must be performed by the FTL. So, the security functions of RoT cannot be bypassed easily. As a compute unit independent of the host device, FBRoT may isolate the potential malicious attacks from the host effectively. Since the implementation is based on reusing flash’s inherent computing power, FBRoT does not need to introduce additional hardware. Thanks to flash’s convenient storage read/write capability, we have also designed the RoT update mechanism for FBRoT, which may make different IoT terminal tenants to build their own proprietary trust chains. Evaluation of the FBRoT prototype system shows that FBRoT incurs reasonable overhead, making it a practical security solution for resource-constrained IoT terminals.“

R&D: Enhanced LDPC Coding for 3D TLC NAND Flash Memory, Leveraging RBER Difference From Intra-Layer Variation

Proposed LVLDPC scheme establishes the correlation between inter-layer interference and raw bit error rate (RBER) based on a neural network model.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems has published an article written by Lanlan Cui, School of Computer Science and Engineering, Xi’an University of Technology, XI’AN, China, and China-ASEAN Information Harbor Co., Ltd, Nanning, China, Fei Wu, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China, Meng Zhang, School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, China, Zhanzhan Zhao, Xuan Zhang, and Kun Jiang, School of Computer Science and Engineering, Xi’an University of Technology, XI’AN, China, and Changsheng Xie, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China.

Abstract: “NAND flash memory employs high code rate low-density parity-check (LDPC) codes to reduce the amount of redundant data that must be added. When the code rate is high, although the redundancy space is small, the error correction capability is inferior to medium or low code rate LDPC. RBER varies among the storage layers for 3D triple-level cell (TLC) NAND flash memory, which increases the frequency of read retry operations. Repeatedly initiating read retry seriously increases the decoding latency and decreases the performance of the 3D TLC NAND flash memory. To alleviate this problem, this article proposes Intra-Layer Variation aware LDPC coding, called LVLDPC. The proposed LVLDPC scheme establishes the correlation between inter-layer interference and raw bit error rate (RBER) based on a neural network model. By analyzing and predicting RBER through the neural network model, we are able to categorize RBER into distinct levels. Then, we then select LDPC codes with appropriate error correction capabilities to decode data with varying levels of RBER. Through this scheme, we don’t need to start read retry when RBER <1.56×10-2. The iteration number is reduced by 67% in total. This scheme only causes 1.15% space overhead, which is negligible. For the stage with high RBER, the number of iterations of LVLDPC is still large, and the extended LVLDPC scheme (eLVLDPC) is further proposed to reduce the use of high code rate and reduce the number of iterations by 19.1%, expanding the correctable RBER threshold to 2.68×10-2.“

R&D: Investigation of L-shaped Split-gate eFlash Memory with Enhanced Gate coupling in 55nm Node

Self-aligned split-gate floating-gate (FG) NOR-type flash memory cell and array have been proposed under a 55 nm node

Applied Physics Letters has published an article written by Wanyi Ling, Kun Ren, Dianyu Qi, College of Integrated Circuits, Zhejiang University, Hangzhou 310000, China, Yongyu Wu, College of Integrated Circuits, Zhejiang University, Hangzhou 310000, China, and Zhejiang ICsprout Semiconductor, Hangzhou 311200, China, Guangji Li, Miao Zhou, Qingshuang Xu, Xuan Li, Zhenghui Xia, Zhejiang ICsprout Semiconductor, Hangzhou 311200, China, Dertsyr Fan, Ichun Chuang, TzungWen Cheng, Chenming Tsai, IOTMemory Technology Inc., Taipei City 10592, Taiwan, and Dawei Gao, College of Integrated Circuits, Zhejiang University, Hangzhou 310000, China, and Zhejiang ICsprout Semiconductor, Hangzhou 311200, China.

Abstract: “As data processing demands increase, embedded flash is advancing toward low power consumption, low manufacturing cost, and high operation speed, as well as large memory windows (MW). A self-aligned split-gate floating-gate (FG) NOR-type flash memory cell and array have been proposed under a 55 nm node. Low-voltage erase and high-speed program operation have been achieved owing to a low EP-to-FG coupling ratio of 0.09 and a high CG-to-FG coupling ratio of 0.67, respectively. Moreover, up to 8 masks can be reduced in our low-cost process, as compared to that of the third-generation SuperFlash. Additionally, close to 5-bit states have been realized in the large MW of 7.1 V in a single-bit cell, which is mostly attributed to the threshold voltage (V_th) tuning by drain-side dual-pocket implantation.“