Astera Labs Assigned Three Patents

SSD-form-factor memory-expansion cartridge with field-replaceable DRAM modules
Astera Labs, Inc., San Jose, CA, has been assigned a patent (12393350) developed by Sharma; Avinash R., San Francisco, CA, for a “SSD-form-factor memory-expansion cartridge with field-replaceable DRAM modules.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hot-swappable DRAM cartridge implemented in a standards-compliant SSD form-factor has an access panel that opens to enable removal and insertion of socketed DRAM memory modules. In at least some implementations, the DRAM cartridge complies with form-factor, protocol, connector, and pin-out/signal specifications set forth in one or more Enterprise and Data Center Standard Form Factor (EDSFF) specifications promulgated by Storage Networking Industry Association (SNIA) including, for example and without limitation, form-factor specifications set forth in EDSFF standards E3.S, E3.S 2T, E3.L and E3.L 2T.”

The patent application was filed on 2023-03-28 (18/127643).

High-speed DIMM slot terminator
Astera Labs, Inc., San Jose, CA, has been assigned a patent (12367168) developed by Cananzi; David A., Santa Clara, CA, Yang; Long, Pleasanton, CA, and Xue; Liang, Los Altos, CA, for a “high-speed DIMM slot terminator.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A motherboard implementing a T-topology bus architecture between a host controller and two or more DDR5 DIMM slots is combined with one or more DIMM terminator cards installed in at least one of the DDR5 DIMM slots to increase the performance of DDR5 DIMM memory accesses.”

The patent application was filed on 2023-10-10 (18/378523).

Virtual metadata storage
Astera Labs, Inc., San Jose, CA, has been assigned a patent (12277350) developed by Mohan; Jitendra, Santa Clara, CA, Provine; Justina, Fremont, CA, Tran; Anh T., Elk Grove, CA, Han; Ken (Keqin), Fremont, CA, and Musoll; Enrique, San Jose, CA, for a “virtual metadata storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A decoding engine within an integrated-circuit (IC) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. Each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. Output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.”

The patent application was filed on 2023-10-30 (18/385021).