Silicon Storage Technology Assigned Patent
Grouping and error correction for NVM cells
By Francis Pelletier | March 3, 2025 at 2:00 pmSilicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (12229004) developed by Tran; Hieu Van, San Jose, CA, for “grouping and error correction for non-volatile memory cells.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “Numerous examples are disclosed of an improved grouping and error correction system for non-volatile memory cells. In one example, a system comprises a memory array comprising non-volatile memory cells arranged into rows and columns, wherein a non-volatile memory cell of the memory array stores a first bit of a first data grouping and a second bit of a second data grouping, and wherein the first grouping is backed by a first ECC block and the second grouping is backed by a second ECC block.”
The patent application was filed on 2023-02-06 (18/106421).











