R&D: Microarchitecture Design and Verification of NAND Flash Memory Controller using System Verilog

IEEE Xplore has published, in 2024 Asia Pacific Conference on Innovation in Technology (APCIT) proceedings, an article written by Harshitha K; Rithik Raj G; Santhosh G H; Subbarahul L S; Gufran Afrudi S, Department of Electronics and Communication Engineering, Vidyavardhaka College of Engineering, Mysuru, India.

Abstract: “Flash memory, it is NOR or NAND in structure, is a non-volatile memory, the NAND Flash is known for its compact size and high speeds for page accesses. This is especially important in applications where the smallest footprint offers the highest-density memory. Our project involves designing a NAND FLASH memory controller for verification purposes. One of our main objectives is to explore System Verilog for verification which also includes the design and implementation of the generator, driver, monitor, and scoreboard. Our approach combines hardware and software engineering to address the challenges of NAND flash memory controllers, ensuring compatibility withvarious NAND flash memory types. The optimization of data transfer rates, error correction, wear leveling, and performance will result in a NAND Flash Memory Controller that sets new standards in NAND flash memory technology. In summary, our project aims to revolutionize NAND flash memory storage, providing efficient, reliable, and cost-effective solutions for applications, from consumer devices to data centers.“