R&D: Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications

IEEE Transactions on Nanotechnology has published an article written by Avinash Lahgere, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India, Alok Kumar Kamal, Department of Electrical/Electronics Engineering ABV-IIITM, Gwalior, India, and Rishu Kumar, Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India.

Abstract: “In this article, we have reported a tunnel field effect transistor (TFET) based unified random access memory (T-URAM), where nonvolatile memory (NVM) and single transistor (1T) DRAM are integrated into a single TFET device. The proposed T-URAM uses a band-to-band tunneling (BTBT) conduction mechanism for programming the NVM and 1T DRAM, in contrast to previously published URAMs. The application of BTBT results in two major advantages: (1) the need for low supply voltage, and (2) disturbancefree NVM operation. Moreover, the T-URAM also exhibits interference-free memory operation due to the use of separate gates for the NVM, and 1T DRAM, respectively. The simulation results reveal that the T-URAM demands 1.5× to 4.5× less supply voltage as compared to the published URAMs. The retention time (RT) of T-URAM during 1T DRAM mode at 358 K is found to be 500 ms, which is ∼ 62.5×, and ∼ 7.8× higher than the buried n-well bulk FinFET URAM, and ITRS prediction, respectively. Moreover, at gate length of 50 nm, the RT of the T-URAM during NVM mode is the same as in the case of the past reported URAMs. In addition, the sense margin of the T-URAM during 1T DRAM mode at 358 K is found to be ∼ 1.9 μA/μm, which is ∼ 7.6× higher than the TFT-based URAM. Also, we have shown a possible way to implement a 2×2 crossbar memory array using the proposed memory. Therefore, the results presented in this paper will pave the way for designing futuristic low-power multi-purpose embedded memory.“