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Silicon Storage Technology Assigned Patent

Method of determining defective die containing NVM cells

Silicon Storage Technology, Inc., San Jose, CA, , a Microchip Technology Inc. company, has been assigned a patent (12020762) developed by Tkachev; Yuri, Sunnyvale, CA, Kim; Jinho, Saratoga, CA, Fung; Cynthia, San Jose, CA, Festes; Gilles, Fuveau, France, Bertello; Bernard, Bouches du Rhones, France, Ghazavi; Parviz, San Jose, CA, Villard; Bruno, Aix en Provence, France, Thiery; Jean Francois, Vaucluse, France, Decobert; Catherine, Pourrieres, France, Jourba; Serguei, Aix en Provence, France, Luo; Fan, Fremont, CA, Tee; Latt, San Francisco, CA, and Do; Nhan, Saratoga, CA, for a method of determining defective die containing non-volatile memory cells.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1. A second read operation is performed to determine a second number N2 of the memory cells having a read current not exceeding a target read current RC2. The target read current RC2 is equal to the lowest read current RC1 plus a predetermined current value. The die is determined to be acceptable if the second number N2 is determined to exceed the first number N1 plus a predetermined number. The die is determined to be defective if the second number N2 is determined not to exceed the first number N1 plus the predetermined number.

The patent application was filed on 2022-01-14 (17/576754).

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