STMicroelectronics Assigned Two Patents

Static random access memory supporting single clock cycle read-modify-write operation
STMicroelectronics International N.V., Geneva, Switzerland, has been assigned a patent (12040013) developed by Verma; Praveen Kumar, Greater Noida, India, and Rawat; Harsh, Faridabad, India, for a “static random access memory supporting a single clock cycle read-modify-write operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.”

The patent application was filed on 2022-07-11 (17/861384).

Data memory access collision manager, device and method
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (12014084) developed by Disegni; Fabio Enrico Carlo, Spino d’Adda, Italy, Goller; Federico, Turin, Italy, Falanga; Dario, Vimercate, Italy, Febbrarino; Michele, Bagheria, Italy, and Montanaro; Massimo, Cava Manara, Italy, for “data memory access collision manager, device and method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.”

The patent application was filed on 2022-02-10 (17/669085).