Sunrise Memory Assigned Three Patents

Quasi-volatile memory device with back-channel usage
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11954363) developed by Norman, Robert D., Pendleton, OR, and Harari, Eli, Saratoga, CA, for a “quasi-volatile memory device with a back-channel usage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.“

The patent application was filed on 2022-03-07 (17/688095).

Thin-film storage transistors in 3D array of NOR memory strings and process for fabricating
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11937424) developed by Herner, Scott Brad, Portland, OR, and Harari, Eli, Saratoga, CA, for “thin-film storage transistors in 3D array of NOR memory strings and process for fabricating.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate, (b) a first semiconductor layer of a first conductivity having an opening therein, (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer, (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer, and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.“

The patent application was filed on 2021-08-26 (17/458029).

Process for 3D array of horizontal NOR-type memory strings
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11917821) developed by Purayath, Vinod, Sedona, AZ, and Chien, Wu-Yi Henry, San Jose, CA, for a “process for 3D array of horizontal NOR-type memory strings.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.“

The patent application was filed on 2021-11-16 (17/527972).