R&D: 13.3 A 280-Layer 1Tb 4b/Cell 3D-NAND Flash Memory with 28.5Gb/mm2 Areal Density and 3.2GB/s High-Speed IO Rate

IEEE Xplore has published, in 2024 IEEE International Solid-State Circuits Conference (ISSCC) proceedings,an article written by Wontaeck Jung; Hyunggon Kim; Do-Bin Kim; Tae-Hyun Kim; Namhee Lee; Dongjin Shin; Minyoung Kim; Youngsik Rho; Hun-Jong Lee; Yujin Hyun; Jaeyoung Park; Taekyung Kim; Hwiwon Kim; Gyeongwon Lee; Jisang Lee; Joonsuc Jang; Jungmin Park; Sion Kim; Su Chang Jeon; Suyong Kim; Jung-Ho Song; Min-Seok Kim; Taesung Lee; Byung-Kwan Chun; Tongsung Kim; Young Gyu Lee; Hokil Lee; Soowoong Lee; Hwaseok Lee; Dooho Cho; Sang-Wan Nam; Yeomyung Kim; Kunyong Yoon; Yoonjae Lee; Sunghoon Kim; Jungseok Hwang; Raehyun Song; Hyunsik Jang; Jaeick Son; Hongsoo Jeon; Myunghun Lee; Mookyung Lee; Kisung Kim; Eungsuk Lee; Myeongwoo Lee; Sungkyu Jo; Chan Ho Kim; Jong Chul Park; Kyunghwa Yun; Soonock Seol; Ji-Ho Cho; Seungjae Lee; Jin-Yub Lee; and Sung-Hoi Hur; Samsung Electronics, Hwaseong, Korea.

Abstract: “3D-NAND Flash memory is evaluated as a key device that is handling the explosive data growth, showing steady bit growth and areal density increases >30% every year. In particular, the 4b/cell (QLC) 3D-NAND technology is appearing to be one of the most promising solutions to meet the market demand with excellent cost effectiveness, while QLC technology is being gradually adopted by various storage applications [1]. However, there are several challenges that need addressing so that QLC technology is adopted rapidly by the market: (1) is the reprogram with on-chip buffered program (OBP) [2], and (2) the low performance caused by the 16-state verify.“