R&D: Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3D NAND Flash Memory

IEEE Transactions on Electron Devices has published an article written by Kihoon Nam, Chanyang Park, Donghyun Kim, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea, Seonhaeng Lee, Namhyun Lee, and Rock-Hyun Baek, Memory Division, Samsung Electronics Company Ltd., Hwaseong, South Korea.

Abstract: “We propose a novel bidirectional precharge and negative bias (BPNB) scheme to suppress the program disturbance of 3-D NAND flash memory. The BPNB scheme was characterized by the application of precharge bias in both directions of a bitline (BL) and common source line (CSL), followed by a negative bias applied to the unselected string select line and ground select line (GSL). Compared to the conventional scheme, the proposed BPNB scheme reduced Y -mode disturbance by 78% and did not degrade the threshold voltage shift ( ΔVth ) of the target cell during measured incremental step pulse programming (ISPP). Moreover, it was fully validated on the word line (WL) location, target cell, and different disturbance modes. We also determined the optimal negative bias and precharge time. Additionally, from a technology computer-aided design (TCAD) simulation, the BPNB scheme had a high channel potential level of unselected strings because of the enhanced self-boosting effect. Overall, the BPNB scheme is a promising and compatible solution for program disturbance suppression in 3-D NAND flash memory.“