Western Digital Technologies Assigned Sixteen Patents

Dynamic valley searching in solid drives
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11468953) developed by Singidi, Harish, Fremont, CA, Banerjee, Amiya, Bangalore, India, and Gupta, Shantanu, Fremont, CA, for a “sequence-controlled polymer random access memory storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device can reorganize a sequentially performed calibration task and delegate vario steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, th reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to e less memory during intermediate multi-pass programming steps.”

The patent application was filed on 2021-03-10 (17/197488).

Expandable memory for use with solid systems and devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11467743) developed by Sharoni, Liran, Hod Hasharon, Israel, and Shaharabany, Amir, Kochav Yair, Israel, for an “expandable memory for use with solid systems and devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure describes technologies and techniques for e by a data storage controller—such as a controller for e with a NAND or other non-volatile memory (NVM)—to provide a er-expandable memory space. In examples described herein, a ctomer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the ctomer may expand the er-accessible memory space. In one example, the ctomer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then e the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.”

The patent application was filed on 2021-04-01 (17/220828).

Remote grant of access to locked storage device
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11469885) developed by Mastenbrook, Brian Edward, Fremont, CA, and Klapman, Matthew Harris, San Jose, CA, for a “remote grant of access to locked data storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed herein is a data storage device with storage medium that stores encrypted er content data. A cryptography engine es a cryptographic key to decrypt the encrypted er content data. An access controller receives, from a er device, a request to register the er device and generates a challenge for a manager device. The manager device is located remotely from the data storage device. The controller sends, to the er device, the challenge for the manager device, receives, from the er device, a response calculated by the manager device to approve the request to register, calculates the cryptographic key based at least partly on the response calculated by the manager device, and creates and stores authorization data associated with the er device. The authorisation data indicates the cryptographic key, to register the er device with the data storage device.”

The patent application was filed on 2020-01-09 (16/739015).

Predictive performance indicator for storage devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11467942) developed by Lavrentiev, Michael, Milpitas, CA, Ravimohan, Narendhiran Chinnaanangur, C, Meenakshi, Bangalore, India, for a “predictive performance indicator for storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for predictive performance indicators for storage devices are described. The data storage device may process host storage operations and maintenance operations that impact real-time performance. A performance value and corresponding threshold may be determined. Increases in maintenance operations and resulting changes in the performance value may be predicted. When the predicted change in performance value crosses the performance threshold, the host device may be notified.”

The patent application was filed on 2021-02-23 (17/182574).

Identify aggressor blocks caing back to back erase failure
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11467744) developed by Arora, Nikhil, Arora, Lovleen, Sankule, Sourabh, and Hiware, Sameer, Karnataka, India, for a “system to identify aggressor blocks caing back to back erase failure.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a controller are provided which identifies a bad, open block that caes subsequent erase operations to fail in closed blocks due to charge leakage following a previo program operation in the open block. Each time the controller programs an open block, the controller attempts to erase a plurality of closed blocks following each programming of the open block. When the closed blocks fail to erase, the controller determines whether a number of consecutive erase failures after programming the open block meets a threshold, after which the controller re-attempts to erase the closed blocks. After a successful re-attempt, the controller stores a list of open blocks in memory. In response to repeating these steps a number or plurality of times, the controller stores multiple lists of open blocks in memory, and identifies the single common open block between the multiple lists as a bad block.”

The patent application was filed on 2020-05-27 (16/885160).

Modified distribution of memory device states
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11462279) developed by Banerjee, Amiya, Bhat, Vinayak, Bangalore, India, and Singidi, Harish R., Fremont, CA, for a “modified distribution of memory device states“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory s within the devices. The modified distribution of memory s attempts to minimize the e of memory s that are sceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory s on the lower and upper s within the voltage threshold range of the memory device. The distribution of memory s can be modified though the e of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device s that are configured to reduce exposure to negative effects th prolonging the overall lifespan of the storage device.”

The patent application was filed on 2021-05-13 (17/319756).

Storage with dual submission queue doorbell registers and method for use in multi-tenant system
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11461052) developed by Benisty, Shay, Beer Sheva, Israel, for “storage system with dual submission queue doorbell registers and method for use in a multi-tenant system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system has two submission queue doorbell registers associated with a submission queue in a host. The storage system fetches and executes a command from the submission queue only in response to both submission queue doorbell registers being written. The second submission queue doorbell register may be visible (and directly written to) by the host or invisible (and indirectly written to) by the host. The e of two submission queue doorbell registers for a single submission queue can be ed as a protection mechanism to protect an administration command submission queue of a child controller in a multiple physical function Non-Volatile Memory Express (NVMe) device (MFND).”

The patent application was filed on 2021-04-08 (17/225385).

Memory card operable with multiple host interfaces
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11461260) developed by Pinto, Yoseph, Tel Aviv, Israel, K, Shiva, Peter, Eldhose, and Balakrishnan, Rakesh, Bangalore, India, for a “memory card operable with multiple host interfaces.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory card has a plurality of pads including a first set of pads located to connect with host contacts arranged in a first configuration for communication according to the micro Secure Digital (microSD) standard, a second set of pads located to connect with host contacts arranged in a second configuration for communication according to the Peripheral Component Interface express (PCIe) protocol, and a third set of pads located to connect with host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard. The plurality of pads includes one or more common pads that are common to the second set of pads and the third set of pads.”

The patent application was filed on 2021-02-19 (17/179953).

HAMR head with tapered main pole and heat sink material adjacent pole
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11462243) developed by Matsumoto, Takuya, Asif Bashir, Muhammad, San Jose, CA, Balamane, Hamid, Portola Valley, CA, Vanderheijden, Petr, Cupertino, CA, and Stripe, Barry Ching, San Jose, CA, for a “heat-assisted Magnetic Recording (HAMR) head with tapered main pole and heat sink material adjacent the pole.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A heat-assisted magnetic recording (HAMR) head for recording data in data tracks of a HAMR disk has a gas-bearing slider that supports a near-field transducer (NFT) and a main magnetic pole formed of two layers. The first main pole layer has a cross-track width at the slider’s gas-bearing surface (GBS) that tapers down in the direction towards the NFT where the optical spot is formed. The second main pole layer is located away from the NFT and has a substantially wider cross-track width than the first main pole layer so as to provide sufficient magnetic field for writing. Layers of heat sink material are located on the sloped cross-track sides of the tapered first main pole layer to reduce the temperature and th the likelihood of oxidation of the main pole layers.”

The patent application was filed on 2020-07-30 (16/943995).

Multibody chambered acotic attenuator for storage system
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456020) developed by Niss, David, Boulder, CO, Zebian, Hsam, San Jose, CA, Fisher, Dana, Berthoud, CO, and Wilke, Jeffrey, Palmer Lake, CO, for a “multibody chambered acotic attenuator for a data storage system.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data storage system includes a chassis hoing multiple data storage devices, such as hard disk drives, a compartment hoing cooling fans, and an air plenum positioned between the fans and the storage devices. A multibody chambered acotic attenuator, which may be installed in the air plenum, includes a plate part having airflow holes therethrough and may include a convex arched part having airflow holes therethrough and coupled with the plate part to form a chamber. Acotic damping material lines an interior surface of the plate part and the interior and exterior surfaces of the arched part, and the airflow holes of the plate part and of the arched part are not aligned, such that direct acotic emissions and reflections would contact the acotic damping material and a circuito airflow path is provided from the cooling fans to the storage devices, to reduce the acotic sound pressure upon the devices.”

The patent application was filed on 2020-06-30 (16/917534).

Distributed grouped terminations for multiple memory integrated circuit systems
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456022) developed by Contreras, John Thomas, Palo Alto, CA, Rajendra, Srinivas, Milpitas, CA, Mobin, Sayed, San Jose, CA, and Zakai, Rehan Ahmed, San Ramon, CA, for “distributed grouped terminations for multiple memory integrated circuit systems.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to apparates and methods for transmission line termination. In one embodiment an apparat includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.”

The patent application was filed on 2020-06-30 (16/916945).

Zoned space limitation mitigation using sub block mode
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11455244) developed by Tikoo, Rakshit, Sreedhar, Adarsh, Arora, Lovleen, and Srimal, Niraj, Karnataka, India, for a “zoned space limitation mitigation using sub block mode.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a memory and a controller are provided which reduces or eliminates garbage collection in zoned space (ZNS) architectures by mapping zones to sub-blocks of blocks of the memory. Each zone includes a plurality of logical addresses. The controller determines a number of open zones, and maps the open zones to the sub-blocks in response to the number of open zones meeting a threshold. Th, larger numbers of open blocks typically present in ZNS may be reduced, and increased block sizes due to scaling may be accommodated in ZNS. In some aspects, the controller receives a request from a host device to write data associated with the zones in sub-blocks, and maps each of the zones to at least one of the sub-blocks in response to the request. The request may indicate zones are partially uned. Th, out of zone conditions may also be avoided.”

The patent application was filed on 2021-02-19 (17/180625).

Soft information for punctured bit estimation in storage
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11455208) developed by Zamir, Ran, Ramat Gan, Israel, Fainzilber, Omer, Herzliya, Israel, Avraham, David, Even Yehuda, Israel, and Sharon, Eran, Rishon Lezion, Israel, for a “soft information for punctured bit estimation in a data storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword ing the LLR value for the punctured bit.”

The patent application was filed on 2021-02-09 (17/171746).

Command prioritization to reduce latencies of zone commands
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11455124) developed by Agarwal, Dinesh Kumar, and Sharma, Amit, Karnataka, India, for a “command prioritization to reduce latencies of zone commands.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a memory and a controller are provided which re-prioritize commands based on zone properties. The controller receives from a host commands associated with a plurality of zones, allocates the memory into a plurality of zone resources based on zone properties indicated by the host for the zones, and identifies a utilization of the memory for one of the zones. The controller changes a priority order of the commands based on the zone properties and the utilization for the one of the zones. The controller then executes the commands in the memory or zone resources according to the priority order. As a result, execution of commands may be balanced between zones and lower latencies may be achieved overall for each zone. Improved performance or throughput of the storage device in handling zone commands may therefore result.”

The patent application was filed on 2021-02-19 (17/180642).

Fixed size soft bit lossy compression in flash memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456754) developed by Zamir, Ran, Ramat Gan, Israel, Sharon, Eran, Rishon Lezion, Israel, Alrod, Idan, Herzeliya, Israel, Bazarsky, Alexander Holon, Israel, Li, Yan, Milpitas, CA, and Sravan, A Harihara, Bangalore, India, for a “fixed size soft bit lossy compression in flash memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.”

The patent application was filed on 2021-02-17 (17/177940).

Relinking scheme in sub-block mode
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456050) developed by Chandramani, and Shirpimutt, Sagar, Bangalore, India, for a “relinking scheme in sub-block mode.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Th, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.”

The patent application was filed on 2021-02-24 (17/184375).