United Microelectronics Assigned Fourteen Patents

NVM and forming method
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11557598) developed by Wu, Tsung-Lin, Singapore, Singapore, for “non-volatile memory and forming method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory includes a substrate, a plurality of gate stacked strips and a plurality of contact plugs. The substrate includes a plurality of diffusion strips. The plurality of gate stacked strips are disposed over the diffusion strips, wherein each of the gate stacked strips includes a charge storage layer and a gate conductor layer stacked from bottom to top. The plurality of contact plugs are disposed on the diffusion strips between the gate stacked strips, wherein a sidewall of each of the gate conductor layer beside the contact plugs and above the diffusion strips has a step profile.”

The patent application was filed on 2022-01-11 (17/573578).

Flash memory cell and forming method
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11552088) developed by Hung, Chia-Min, Shih, Ping-Chia, Kuo, Che-Hao, Tainan, Taiwan, Chuang, Kuei-Ya, Chiayi County, Taiwan, Liu, Ssu-Yin, Kaohsiung, Taiwan, Chen, Po-Hsien, Tainan,Taiwan, and Liao, Wan-Chun, Hsinchu County, Taiwan, for “flash memory cell and forming method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.”

The patent application was filed on 2021-03-11 (17/198268).

NVM device and method for fabricating
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11532716) developed by Wang, Chia-Wen, Tainan,Taiwan, Chen, Chien-Hung, Hsinchu, Taiwan, Huang, Chia-Hui, Hsueh, Jen Yang, Chou, Ling Hsiu, and Hsu, Chih-Yang, Tainan, Taiwan, for “non-volatile memory device and method for fabricating the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.”

The patent application was filed on 2020-02-18 (16/793930).

System architecture, structure and method for hybrid random access memory in system-on-chip
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11522013) developed by Hsu, Po-Kai, Tainan, Taiwan, Wang, Hui-Lin, Taipei, Taiwan, Hsu, Ching-Hua, Kaohsiung, Taiwan, Lin, Yi-Yu, Taichung, Taiwan, Fan, Ju-Chun, Tainan, Taiwan, and Chen, Hung-Yueh, Hsinchu, Taiwan, for “system architecture, structure and method for hybrid random access memory in a system-on-chip.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.”

The patent application was filed on 2020-09-27 (17/033901).

Semiconductor memory device
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11515316) developed by Chen, Tzu-Ping, Hsinchu County, Taiwan, for a “semiconductor memory device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.”

The patent application was filed on 2020-11-24 (17/103872).

Semiconductor memory device and manufacturing
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11456305) developed by Chen, Chih-Jung, Hsinchu County, Taiwan, and Shuai, Hung-Hsun, Tainan, Taiwan, for “semiconductor memory device and manufacturing method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.”

The patent application was filed on 2020-08-27 (17/005285).

Semiconductor memory cell and forming method
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11450670) developed by Lee, Kuo-Hsing, Hsinchu County, Taiwan, Lee, Kun-Hsien, Hsueh, Sheng-Yuan, Wong, Chang-Chien, Tseng, Ching-Hsiang, Tainan, Taiwan, Wu, Tsung-Hsun, Kaohsiung, Taiwan, Pai, Chi-Horn, Tainan, Taiwan, and Hsu, Shih-Chieh, New Taipei, Taiwan, for “semiconductor memory cell and the forming method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.”

The patent application was filed on 2021-04-14 (17/230975).

Semiconductor device and method for forming
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11437436) developed by Wang, Wen-Jen, Tainan, Taiwan, Cheng, Chun-Hung, Kaohsiung, Taiwan, and Wang, Chuan-Fu, Miaoli County, Taiwan, for “semiconductor device and method for forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.”

The patent application was filed on 2020-10-29 (17/084609).

Split-gate flash memory cell and fabrication method
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11437475) developed by Lee, Chih-Haw, and Chen, Tzu-Ping, Hsinchu County, Taiwan, for “split-gate flash memory cell and fabrication method thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.”

The patent application was filed on 2021-02-18 (17/178269).

Cell trace circuit for measuring I-V property of memory cell
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11417412) developed by Chen, Chung-Hao, Taoyuan, Taiwan, and Lu, Hsiao-Hua, Hsinchu County, Taiwan, for a “cell trace circuit for measuring I-V property of memory cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.”

The patent application was filed on 2021-03-01 (17/189094).

Memory cell and fabricating method
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11417742) developed by Pan, Chih-Hao, Huang, Chi-Cheng, Kaohsiung, Taiwan, Li, Kuo-Lung, Wang, Szu-Ping, Chen, Po-Hsuan, Tainan, Taiwan, and Cheng, Chao-Sheng, Taichung, Taiwan, for “memory cell and fabricating method of the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.”

The patent application was filed on 2021-03-31 (17/219829).

Fabricating flash memory
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11417734) developed by Chen, Chih-Jung, Hsinchu County, Taiwan, and Yeh, Yu-Jen, Taichung, Taiwan, for a “method for fabricating flash memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.”

The patent application was filed on 2019-10-31 (16/670870).

Memory and method for fabricating
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11387337) developed by Huang, Chun-Sung, Changhua County, Taiwan, Wang, Shen-De, Hsinchu County, Taiwan, Hsu, Chia-Ching, Yunlin County, Taiwan, and Xiang, Wang, Singapore, Singapore, for “memory device and method for fabricating the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.”

The patent application was filed on 2020-12-24 (17/134131).

Fabricating flash memory
United Microelectronics Corp., Hsin-Chu, Taiwan, has been assigned a patent (11387241) developed by Chen, Ming-Shing, Tainan, Taiwan, for a “method for fabricating flash memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for fabricating flash memory is provided. A plurality of floating gate structures is formed on a gate dielectric layer in the memory device region of a substrate. The protective spacers are formed on two opposite sidewalls of each floating gate structure. A polysilicon gate structures are formed on the logic device region and a polysilicon control gate structure with an opening are formed on the memory device region to cover two adjacent floating gate structures, wherein the two protective spacers facing each other between two adjacent floating gate structures are exposed by the opening, and then the exposed protective spacer are removed. An ion implantation is performed on the substrate to form a source region between the two adjacent floating gate structures on each cell area. There will be no polysilicon material residue in the memory device region or pitting/undercutting phenomenon in the logic device region.”

The patent application was filed on 2020-09-22 17/027730).