Tokyo Electron Assigned Patent

Tokyo Electron Limited, Tokyo, Japan, has been assigned a patent (11557655) developed by Fulford, H. Jim, Marianna, FL, and Gardner, Mark, Cedar Creek, TX, for “device and method of forming with three-dimensional memory and three-dimensional logic.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.”

The patent application was filed on 2020-03-23 (16/827101).