iCometrue Assigned Two Patents

Logic drive based on standardized commodity programmable logic semiconductor IC chips
iCometrue Company Ltd., Hsin-Chu County, Taiwan, has been assigned a patent (11545477) developed by Lee, Jin-Yuan, and Lin, Mou-Shiung, Hsinchu, Taiwan, for a “logic drive based on standardized commodity programmable logic semiconductor ic chips.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers, a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer, multiple first metal bumps between the interposer and the FPGA IC chip, a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps, a non-volatile memory (NVM) IC chip over the interposer, multiple second metal bumps between the interposer and the NVM IC chip, and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.”

The patent application was filed on 2021-02-07 (17/169537).

Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
iCometrue Company Ltd., Hsin-Chu County, Taiwan, has been assigned a patent (11309334) developed by Lin, Mou-Shiung, and Lee, Jin-Yuan, Hsinchu, Taiwan, for a “logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A multi-chip package includes: an interposer, a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation, and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.”

The patent application was filed on 2020-11-22 (17/100937).