Western Digital Technologies Assigned Nineteen Patents

Adaptive soft-bit compression in flash memory
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456758) developed by Zamir, Ran, Ramat Gan, Israel, Sharon, Eran, Rishon Lezion, Israel, and Bazarsky, Alexander, Holon, Israel, for an “adaptive soft-bit compression in flash memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory includes, in one embodiment, NAND elements, read/write circuitry, and compressed soft-bit circuitry. The compressed soft-bit circuitry is configured to determine or receive one or more NAND conditions and then determine a soft-bit delta and select a compression scheme based on the NAND conditions. The read/write circuitry is configured to read a set of hard bits from the NAND elements and sense a first set of soft-bits ing the determined soft-bit delta while reading the set of hard bits from the NAND elements. The first set of soft-bits has a first fixed size, and each soft-bit of the first set of soft-bits indicates a reliability of a corresponding hard bit of the set of hard bits. The compressed soft-bit circuitry is also configured to generate a second set of soft-bits based on the selected compression scheme and output the second set of soft-bits to a controller.”

The patent application was filed on 2021-04-23 (17/239057).

Shared disk configuration in multiple actuator HDD
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456009) developed by Liu, Yanning, San Jose, CA, for a “shared disk configuration in a multiple actuator hard disk drive.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A multiple-actuator hard disk drive includes multiple head-stack assemblies (HSA) and a disk stack including a shared disk operated upon by both of the HSAs. Generally to provide more space between the HSAs such as for routing electrical traces, the distance between the shared disk and each of the upper and lower adjacent disks is greater than the distance between each of the upper and lower adjacent disks and the next adjacent disk. Each arm tip of the arms operating upon the shared disk may be thicker than other arm(s) operating upon other disks in the stack, so that the z-height between each head slider and corresponding disk surface is maintained in view of the differing disk spacing. Spension tails for the arms that operate on the shared disk may be biased to offset away from the shared disk to provide for more clearance between the HSAs.”

The patent application was filed on 2021-09-14 (17/475217).

Repeatable runout compensation value generation
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11456014) developed by Chen, Zaifeng, Rancho Palos Verdes, CA, and Ji, Chuanwen, Irvine, CA, for a “repeatable runout compensation value generation.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Generating a hard disk drive (HDD) data track repeatable runout (RRO) compensation value for a target track involves querying at least one RRO table for a closest track to the target track external servo target (EST) and identifying an EST.sub.x corresponding to the closest track, computing a first absolute value of the difference between the EST and the EST.sub.x, and responsive to the first absolute value being less than an approximation threshold, setting the RRO compensation value for the target track to the RRO compensation value for the closest track. Else, querying the RRO table(s) for each adjacent track to the target track, computing the difference between the ESTs for the adjacent tracks, and responsive to the second absolute value being less than an interpolation threshold, determining an RRO compensation value for the target track based on RRO compensation values corresponding to the adjacent tracks.”

The patent application was filed on 2021-10-05 (17/494825).

Memory card system with improved password reset method
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11449599) developed by Singla, Lovish, Vinayak, Prathika, Singh, Sandeep, and Kumar, Akash, Karnataka, India, for a “memory card system with improved password reset method.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, devices, and methods for resetting a current password of a memory device or a memory card system. The method includes receiving a data block including a content field, a combined password length of a user-defined current password and a new password, and a user-defined password length of the new password. The content field includes the user-defined current password and the new password. The method also includes determining a system calculated password length of the new password based at least on the combined password length and a length of the current password. The method further includes matching the system calculated password length and the user-defined password length and comparing the user-defined current password with the current password. The method also includes replacing or resetting the current password with the new password based on a result of the matching and a result of the comparing.”

The patent application was filed on 2019-09-20 (16/577055).

Storage device with syndrome weight minimization for data alignment
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11449236) developed by Avraham, David, Even Yehuda, Israel, Fainzilber, Omer, Herzliya, Israel, Shlick, Mark, Ganey-Tikva, Israel, and Mark, Yoav, Tel-Aviv, Israel, for a “data storage device with syndrome weight minimization for data alignment.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjted codeword.”

The patent application was filed on 2020-05-01 (16/864257).

Power target calibration for controlling drive-to-drive performance variations in SSDs
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11449245) developed by Brittner, Rodney, San Jose, CA, and Tidwell, Reed, Centerville, UT, for a “power target calibration for controlling drive-to-drive performance variations in solid drives (SSDs).”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “To provide more uniform performance levels for solid drive (SSDs), the static power level ed by an SSD in an idle is measured and ed to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and ed to offset a received power supply level for e on the drive. For a data storage system of multiple SSDs, a common scaling factor can be ed to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.”

The patent application was filed on 2019-06-13 (16/440472).

Enhanced read-ahead capability for storage devices
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11449428) developed by Benisty, Shay, Beer Sheeva, Israel, Navon, Ariel, Revava, Israel, and Eliash, Tomer, Sunnyvale, CA, for an “enhanced read-ahead capability for storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In the context of data storage, an approach to pre-fetching data prior to a read request involves receiving a read request and a next read request, and updating metadata corresponding to the read request with a next data storage address corresponding to the next read request. Responsive to again receiving the read request at a later time, the next data storage address can be read from the read request metadata and the next data can be pre-fetched from the next data storage address in advance of processing a following read request. Furthermore, the next data can be pre-fetched during read queue idle time and stored in a cache buffer, in anticipation of another incoming next read request, responsive to which the next data can be returned to the host from the buffer rather than from a read of non-volatile memory.”

The patent application was filed on 2020-09-10 (17/017626).

Identification and classification of write stream priority
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11449443) developed by Kragel, Oleg, Tang, Xiangyu, San Jose, CA, Sivasankaran, Vijay, Dublin, CA, and Palityka, Mikhail, Oakville, CA, for an “identification and classification of write stream priority.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone age or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority stat of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjted before, during, or after priority evaluation. The continuo operation of this process can allow for adjtments being made to priority levels within the storage device that may further increase total operational efficiency.”

The patent application was filed on 2021-02-26 (17/187046).

Storage systems and methods for optimized scheduling of background management operations
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11442635) developed by Eliash, Tomer Tzvi, Kfar Saba, Isarel, Bazarsky, Alexander, Holon, Israel, and Grossman, Yuval, Kiryat Ono, Israel, for “data storage systems and methods for optimized scheduling of background management operations.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatus, media, methods, and systems for data storage systems and methods for optimized scheduling of background management operations. A data storage system may comprise a controller. The controller is configured to determine a timeout value of an adaptive timeout parameter of the data storage system. The controller is configured to determine whether a first host operation is received. The controller is configured to, when the first host operation is not received, determine whether the timeout value satisfies a threshold value. The controller is configured to, when the timeout value satisfies the threshold value, cae one or more background management operations to be executed at the data storage system.”

The patent application was filed on 2019-01-10 (16/245173).

Adaptive context metadata message for optimized two-chip performance
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11442852) developed by Lindberg, Todd, Ellis, Robert, Phoenix, AZ, O’Toole, Kevin, Chandler, AZ, and Shivhare, Vivek, San Jose, CA, for an “adaptive context metadata message for optimized two-chip performance.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.”

The patent application was filed on 2020-06-25 (16/911787).

Spinel containing magnetic tunnel junction and method of making
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11443790) developed by Prasad, Bhagwati, San Jose, CA, Stewart, Derek, Livermore, CA, Carey, Matthew, San Jose, CA, and Santos, Tiffany, Palo Alto, CA, for “spinel containing magnetic tunnel junction and method of making the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A magnetoresistive memory device includes a first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes, from one side to another: a reference layer having a fixed reference magnetization direction, a first spinel layer located including a first polycrystalline spinel material having (001) texture along an axial direction that is perpendicular to an interface with the reference layer, a magnesium oxide layer including a polycrystalline magnesium oxide material having (001) texture along the axial direction, a second spinel layer including a second polycrystalline spinel material having (001) texture along the axial direction, and a ferromagnetic free layer.”

The patent application was filed on 2021-03-04 (17/192354).

Identified zones for optimal parity sharing zones
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11442646) developed by Agarwal, Dinesh Kumar, Bangalore, India, for “identified zones for optimal parity sharing zones.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Storage devices are capable of identifying zones for sharing parity blocks across zones. Active zones may be segregated across multiple active zones having similar zone properties, and grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, storage devices and systems can: (i) maintain independent parity for all zones during initial zone writes (i.e. during an erased when data is written directly to pages and not to the zones), (ii) track zone write pointers and frequency of writes in the zones, (iii) segregate zones with higher correlation and group them together, (iv) utilize these groupings placed across vario channels so that zones with high correlations, comprising of the zones that are written together and at the same rate, share the parity buffers, and (v) load and XOR individual parity buffers for optimal parity sharing across all zones.”

The patent application was filed on 2021-02-26 (17/186764).

Storage and dual-write programming method with reverse order for secondary block
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11442666) developed by Sikarwar, Yogendra Singh, Naghate, Ankit, Giradkar, Milind, Karnataka, India, and Tikoo, Rakshit, Uttar Pradesh, India, for “storage system and dual-write programming method with reverse order for secondary block.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system has a memory with primary and secondary blocks. Data is stored redundantly in the primary and secondary memory blocks but in a different programming order. For example, data is programmed in the first memory block starting at a first wordline and ending at a last wordline, while data is programmed in the second memory block starting at the last wordline and ending at the first wordline.”

The patent application was filed on 2021-02-23 (17/182485).

Storage and method for dynamic selection of host interface
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11442665) developed by Balakrishnan, Rakesh, Peter, Eldhose, K, Shiva, Bengaluru, India, for “storage system and method for dynamic selection of a host interface.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface, in response to receiving the selection of the first host interface, implement the first host interface, after the first host interface has been implemented, receive, from the host, a selection of a second host interface, and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previoly implemented. Other embodiments are provided.”

The patent application was filed on 2021-02-18 (17/178447).

Thermoelectric semiconductor device and method of making
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11444001) developed by Du, Jiandi, Zhang, Yazhou, Zheng, Binbin, Shanghai, China, Chandran, Sundarraj, Tirunelveli, India, Qu, Wenbin, Shanghai, China, and Chiu, Chin-Tien, Taichung, Taiwan, for “thermoelectric semiconductor device and method of making same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.”

The patent application was filed on 2021-05-07 (17/314712).

Read head having one or more antiferromagnetic layers above soft bias side shields, and related methods
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11437061) developed by Le, Quang, Jiang, Hongquan, Hwang, Cherngye, and Takano, Hisashi, San Jose, CA, for “read head having one or more antiferromagnetic layers above soft bias side shields, and related methods.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to read head apparat, and methods of forming read head apparat, for magnetic storage devices, such as magnetic tape drives (e.g., tape drives). In one implementation, a read head for magnetic storage devices includes a lower shield, one or more upper shields, one or more lower leads, and a plurality of upper leads. The read head includes a plurality of read sensors, each read sensor of the plurality of read sensors including a first antiferromagnetic (AFM) layer. The read head includes a plurality of soft bias side shields disposed between and outwardly of the plurality of read sensors. The read head includes one or more second AFM layers disposed above the first AFM layer and the plurality of soft bias side shields along a downtrack direction.”

The patent application was filed on 2021-06-25 (17/359171).

HAMR medium with optical-coupling multilayer between the recording layer and heat-sink layer
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11437064) developed by Jubert, Pierre-Olivier, San Jose, CA, Dorsey, Paul Christopher, Los Altos, CA, and Ho, Hoan Cong, San Jose, CA, for “heat-assisted Magnetic Recording (HAMR) medium with optical-coupling multilayer between the recording layer and heat-sink layer.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A heat-assisted magnetic recording (HAMR) disk has a magnetic recording layer (typically a FePt chemically-ordered alloy), a seed-thermal barrier layer (typically MgO) below the recording layer, a heat-sink layer, and an optical-coupling multilayer of alternating plasmonic and non-plasmonic materials between the heat-sink layer and the seed-thermal barrier layer. Unlike a heat sink layer, the multilayer has very low in-plane and out-of-plane thermal conductivity and th does not function as a heat sink layer. The multilayer’s low thermal conductivity allows the multilayer to also function as a thermal barrier. Due to the plasmonic materials in the multilayer it provides excellent optical coupling with the near-field transducer (NFT) of the HAMR disk drive.”

The patent application was filed on 2021-08-06 (17/395820).

Dynamic ZNS open zone active limit
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11435914) developed by Bazarsky, Alexander, Holon, Israel, Eliash, Tomer, Kfar Saba, Israel, Hahn, Judah Gamliel, Ofra, Israel, Navon, Ariel, Revava, Israel, and Benisty, Shay, Beer Sheva, Israel, for a “dynamic ZNS open zone active limit.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device includes a controller that can dynamically adjt the zone active limit (ZAL) for a zoned space (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.”

The patent application was filed on 2020-03-30 (16/835191).

Moving change log tables to align to zones
Western Digital Technologies, Inc., San Jose, CA, has been assigned a patent (11436153) developed by Helmick, Daniel L., Broomfield, CO, Dancho, Mark, Chandler, AZ, and Jones, Ryan R., Mesa, AZ, for “moving change log tables to align to zones.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure generally relates to methods of operating storage devices. The storage device is comprised of a controller, a random access memory (RAM) unit, and a NVM unit, wherein the NVM unit is comprised of a plurality of zones. The RAM unit comprises a first logical to physical address table and the NVM unit comprises a second logical to physical address table. The zones are partitioned into sections, and each partitioned section aligns with a change log table. Data is written to each zone sequentially, and only one partitioned section is updated at a time for each zone. Each time a zone is erased or written to in the NVM unit, the first logical to physical address table is updated and the second logical to physical address table is periodically updated to match the first logical to physical address table.”

The patent application was filed on 2020-05-26 (16/883901).