R&D: Failure Analysis Challenges of PCM Test Structures With Two Case Studies

Discuss some of failure analysis challenges which have appeared in discrete test structures and test arrays of exploratory PCM program at IBM's Albany AI Hardware Research Center.

This is a Press Release edited by StorageNewsletter.com on December 31, 2021 at 2:00 pm

ASM International has published, in ISTFA (International Symposium for Testing and Failure Analysis) proceedings, an article written by J. Demarest, N. Arnold, K. Brew, V. Chan, IBM, Albany, New York, USA, A. Cote, IBM, East Fishkill, New York, USA, T. Gordon, M. Iwatake, IBM, Albany, New York, USA, G. Lian, IBM, East Fishkill, New York, USA, J. Li, I. OK, S. McDermott, I. Saraf, N. Saulnier, L. Tierney, and A. Varghese, IBM, Albany, New York, USA.

Abstract: “There are several variants of artificial intelligence (AI) hardware structures which are under study by the semiconductor industry as potential future synergistic technology adders to existing complementary metal–oxide–semiconductor (CMOS) designs. This paper will discuss some of the failure analysis challenges which have appeared in discrete test structures and test arrays of an exploratory PCM program at IBM’s Albany AI Hardware Research Center.“