Kioxia Assigned Twenty-One Patents

Storage including nonvolatile memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,132,132) developed by Teranishi, Masaomi, Sato, Keisuke, Sakurai, Shuichi, Yokohama Kanagawa, Japan, and Nakashima, Masahiko, Kawasaki Kanagawa, Japan, for a “storage apparatus including nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage apparatus includes a first memory, which is nonvolatile, a first controller that controls the first memory, a wireless antenna, a second memory, which is operable based on power supplied from the wireless antenna, and a second controller that is operable based on the power supplied from the wireless antenna, and performs communication using the wireless antenna. When performing communication with an external apparatus using the wireless antenna, the second controller performs authentication of the external apparatus, and stores in the second memory an authentication result indicating whether the authentication succeeded or failed. If the authentication result indicates that the authentication succeeded, the second controller permits reading by the external apparatus of first data from the second memory by communication using the wireless antenna or writing by the external apparatus of second data to the second memory by communication using the wireless antenna.”

The patent application was filed on December 23, 2019 (16/725,561).

Semiconductor storage device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,754) developed by Oike, Go, Mie Mie, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.”

The patent application was filed on May 27, 2020 (16/884,347).

Semiconductor storage and manufacturing
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,753) developed by Yamamoto, Koichi, Yokkaichi, Japan, for “semiconductor storage device and semiconductor storage device manufacturing method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device of the embodiment includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a stepped portion in which ends of the plurality of conductive layers are stepped, a pillar penetrating the stacked body, the pillar having a memory cell at a height position of each of the plurality of conductive layers, a contact disposed at the stepped portion, the contact being connected to an n-th conductive layer when counted from a lowermost conductive layer of the plurality of conductive layers, and a region in an, n-1)th conductive layer when counted from the lowermost conductive layer of the plurality of conductive layers, the region being disposed at a position below the contact, the region being insulated from the (n-1)th conductive layer surrounding a periphery.”

The patent application was filed on March 12, 2020 (16/816,374).

Semiconductor device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,711) developed by Shini, Masato, Mie Mie, Japan, for a “semiconductor device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor device includes a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode includes a first surface, a second surface, a third surface, and a fourth surface. The second electrode includes a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is provided between the fourth surface and a portion of the first insulating layer that surrounds the fourth surface, and is provided away from the third surface in the first direction.”

The patent application was filed on March 3, 2020 (16/807,910).

Memory controlling threshold voltage in read operation
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,476) developed by Takizawa, Kazutaka, Yokohama, Japan, Kojima, Yoshihisa, Kawasaki, Japan, Kuroda, Sumio, Yokohama, Japan, and Niijima, Masaaki, Machida, Japan, for “memory system controlling a threshold voltage in a read operation and method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage, and causes the first memory to execute the read operation using the first candidate value as the read voltage.”

The patent application was filed on March 12, 2020 (16/817,371).

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,470) developed by Sako, Mario, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor memory device includes: a first bit line, a first memory cell electrically coupled to the first bit line, and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.”

The patent application was filed on June 15, 2020 (16/902,145).

Resistance change memory and associated methods
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,448) developed by Fujino, Yorinobu, Yokohama Kanagawa, Japan, for “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory device includes a resistance change memory element to which one of a low-resistance state and a high-resistance state is allowed to be set in accordance with a write current, a first transistor including a first gate, and causing a current to flow through the resistance change memory element in a first write period, a voltage holding section holding a first voltage applied to the first gate in the first write period, and a second transistor including a second gate, in which the first voltage held in the voltage holding section is applied to the second gate, thereby causing a current to flow through the resistance change memory element in a second write period after the first write period.”

The patent application was filed on March 12, 2020 (16/817,039).

Semiconductor storage
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,127,441) developed by Utsumi, Tetsuaki, Yokohama Kanagawa, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.”

The patent application was filed on September 2, 2020 (17/010,569).

Method of semiconductor integrated circuit, circuit design, and non-transitory computer-readable medium
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,126,770) developed by Fujiwara, Shintaro, Hiratsuka, Japan, for “method of semiconductor integrated circuit, circuit design system, and non-transitory computer-readable medium.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A design method of a semiconductor integrated circuit according to embodiments includes: creating pseudo-cell information for cells included in cell library information, the pseudo-cell information reflecting the degree of difficulty of pin access that connects wires to pins set in the cells, and using cells with a low difficulty of pin access with reference to the pseudo-cell information in timing optimization.”

The patent application was filed on January 31, 2020 (16/777,987).

Memory having high data transfer efficiency and host controller
Kioxia Corp., Tokyo, Japan , has been assigned a patent (RE48,736) developed by Fujimoto, Akihisa, Yamato, Japan, for “memory system having high data transfer efficiency and host controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.”

The patent application was filed on September 3, 2019 (16/559,092).

Semiconductor device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,121,710) developed by Hirashima, Yasuhiro, Kawasaki Kanagawa, Japan, Koyanagi, Masaru, Ota Tokyo, Japan, and Takayama, Yutaka, Nagoya Aichi, Japan, for a “semiconductor device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.”

The patent application was filed on August 24, 2020 (17/000,708).

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,121,227) developed by Utsumi, Tetsuaki, Yokohama, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor memory device includes: a semiconductor substrate, a memory cell array disposed separately from the semiconductor substrate in a first direction, and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.”

The patent application was filed on September 4, 2020 (17/013,286).

Semiconductor storage
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,120,883) developed by Futatsuyama, Takuya, and Shirakawa, Masanobu, Kanagawa, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor storage device includes a first semiconductor extending above a substrate and including a first part and a second part, a first word line at a first level above the substrate and facing the first part of the first semiconductor, a second word line at the first level above the substrate and facing the second part of the first semiconductor, a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line, and a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line.”

The patent application was filed on September 16, 2020 (17/022,586).

Nonvolatile semiconductor memory device with plurality of memory blocks
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,120,875) developed by Fukano, Gou, Tokyo, Japan, for “nonvolatile semiconductor memory device with a plurality of memory blocks with memory strings and a shared block decoder to allow the number of selection signals to be reduced.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.”

The patent application was filed on January 24, 2020 (16/752,230).

Memory device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,120,866) developed by Iizuka, Takahiko, Takashima, Daisaburo, and Ogiwara, Ryu, Yokohama, Japan, for a “memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a driver that sequentially supplies a first voltage, a second voltage higher than the first voltage, and the first voltage to the bit line, during the writing operation to the first memory cell. The driver supplies a third voltage to the second word line and a fourth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if a data is a first data. The driver supplies a fifth voltage to the second word line and a sixth voltage to the second selecting gate line while changing the voltage of the bit line from the second voltage to the first voltage if the data is a second data. At least the sixth voltage is larger than the fourth voltage or the fifth voltage is larger than the third voltage.”

The patent application was filed on September 9, 2020 (17/015,408).

Magnetic memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,120,858) developed by Ueda, Yoshihiro, and Quinsat, Michael Arnaud, Yokohama Kanagawa, Japan, for a “magnetic memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A magnetic memory according to an embodiment includes: a first wiring, a second wiring, a first switching element disposed between the first wiring and the second wiring, a first magnetic member extending in a first direction and disposed between the first switching element and the second wiring, a third wiring disposed between the first magnetic member and the second wiring, a first magnetoresistive element disposed between the third wiring and the second wiring, and a second switching element disposed between the first magnetoresistive element and the second wiring.”

The patent application was filed on June 29, 2020 (16/914,511).

Memory having plural circuits separately disposed from memories
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,120,842) developed by Kimura, Fuminori, Kamakura Kanagawa, Japan, for a “memory system having plural circuits separately disposed from memories.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.”

The patent application was filed on March 2, 2020 (16/806,997).

Memory system and method of controlling nonvolatile memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,119,701) developed by Kanno, Shinichi, Ota, Japan, for “memory system and method of controlling nonvolatile memory by controlling the writing of data to and reading of data from a plurality of blocks in the nonvalatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller prohibits processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block, on the basis of a plurality of first counter values corresponding to a plurality of blocks in the nonvolatile memory. The controller prohibits release of a region in a buffer that stores data being written or waiting for being written to a write destination block associated with an uncompleted read command, on the basis of a plurality of second counter values corresponding to a plurality of write destination blocks.”

The patent application was filed on March 11, 2020 (16/815,970).

Memory system
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,114,170) developed by Handa, Takaya, Yokohama Kanagawa, Japan, Kojima, Yoshihisa, Kawasaki Kanagawa, Japan, and Iwasaki, Kiyotaka, Yokohama Kanagawa, Japan, for a “memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.”

The patent application was filed on May 28, 2020 (16/886,546).

Non-volatile semiconductor memory device including first memory bunch and second memory bunch
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,114,162) developed by Hosomura, Yoshikazu, Kamakura, Japan, for a “non-volatile semiconductor memory device including a first memory bunch and a second memory bunch.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line, a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line, a common bit line, a first bit line transfer transistor, and a second bit line transfer transistor.”

The patent application was filed on March 6, 2020 (16/810,910).

NAND switch
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,113,222) developed by Law, Sie Pook, San Jose, CA, for a “NAND switch.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. Each of the enable outputs of the switch is connected to an enable input of one of the non-volatile storage units. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.”

The patent application was filed on December 24, 2019 (16/726,763).