Yangtze Memory Technologies Assigned Twenty-One Patents

Testing memory employing limited number of test pins and memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,125,816) developed by Xu, Xiaodong, Zhao, Xiangming, Liu, Shunlin,and Chen, Yi, Wuhan, China, for “method of testing memory device employing limited number of test pins and memory device utilizing same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pinA method is used to test a memory device including a package substrate, a controller die and a memory die. The package substrate includes an isolation pin, a test mode select pin, a test clock pin and a test data pin. The method includes setting the isolation pin to an isolation state to isolate the memory die from the controller die, and when the isolation pin is set to the isolation state, setting the memory die to receive control via the test mode select pin, the test clock pin and the test data pin.”

The patent application was filed on December 23, 2019 (16/726,098).

3D memory device and manufacturing
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,121,152) developed by Wang, Qiguang, Jin, Lei,Zhang, An, and Lu, Jianwei, Wuhan, China, for “three-dimensional memory device and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. An opening is formed penetrating the alternating dielectric stack in a thickness direction of the substrate. A blocking layer is formed on a sidewall of the opening. A trapping layer is formed in the opening, and the trapping layer is formed on the blocking layer. The trapping layer includes a lower portion and an upper portion disposed above the lower portion. A thickness of the upper portion in a horizontal direction is greater than a thickness of the lower portion in the horizontal direction. The thickness distribution of the trapping layer is modified for improving the electrical performance of the 3D memory device.”

The patent application was filed on November 10, 2019 (16/679,265).

3D memory and fabricating
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,121,150) developed by Xiao, Li Hong, and Liu, Jun, Wuhan, China, for “three-dimensional memory devices and fabricating methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate, forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack, forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface, forming a channel layer to cover the functional layer in each channel hole, and forming a filling structure to cover the channel layer and fill each channel hole.”

The patent application was filed on January 9, 2019 (16/243,787).

Marking pattern in forming staircase structure of three-dimensional memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,121,092) developed by Chen, Lin, Liu, Yunfei, and Wang, Meng, Wuhan, China, for “marking pattern in forming staircase structure of three-dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.”

The patent application was filed on August 16, 2019 (16/543,237).

3D memory with support structures in gate line slits and forming
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,114,458) developed by Huo, Zongliang, Yang, Haohao, Xu, Wei, Yan, Ping, Huang, Pan, and Zhou, Wenbin, Wuhan, China, for “three-dimensional memory device with support structures in gate line slits and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.”

The patent application was filed on October 31, 2019 (16/670,594).

Memory stacks having silicon oxynitride gate-to-gate dielectric layers
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,114,456) developed by Xiao, Li Hong, Wuhan, China, for “memory stacks having silicon oxynitride gate-to-gate dielectric layers and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.”

The patent application was filed on June 27, 2019 (16/455,634).

Bonded memory device and fabrication
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,114,453) developed by Yang, Shengwei, Xia, Zhongyi, Han, Kun, Li, Kang, Wang, Xiaoguang, and Zhu, Hongbin, Wuhan, China, for “bonded memory device and fabrication methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.”

The patent application was filed on December 22, 2018 (16/231,481).

Multi-division 3D NAND memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,114,439) developed by Zhang, Zhong, and Li, Yan Ni, Hubei, China, for a “multi-division 3D NAND memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions.”

The patent application was filed on August 27, 2020 (17/004,871).

Computation-in-memory in 3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,114,434) developed by Yang, Shengwei, Xia, Zhongyi, and Han, Kun, Wuhan, China, for a “computation-in-memory in three-dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a first semiconductor structure including a peripheral circuit, a data processing circuit, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. In addition, the 3D memory device includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.”

The patent application was filed on August 15, 2019 (16/542,274).

3D memory with source structure
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,101,286) developed by Huang, Pan, Xu, Wei, Yan, Ping, Xu, Wenxiang, Huo, Zongliang, Zhou, Wenbin, and Xia, Ji, Wuhan, China, for “three-dimensional memory device with source structure and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, and a source structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. At least two of the plurality of source contacts are in contact with and conductively connected to one another.”

The patent application was filed on October 16, 2019 (16/655,157).

3D memory and fabricating
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,094,714) developed by Chen, Liang, Xue, Lei, Liu, Wei, and Huang, Shi Qi, Hubei, China, for “three-dimensional memory devices and fabricating methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.”

The patent application was filed on December 30, 2019 (16/729,865).

3D memory with source contacts connected by adhesion layer
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,094,713) developed by Wang, Qingqing, Xu, Wei, Huang, Pan, Yan, Ping, Huo, Zongliang, and Zhou, Wenbin, Wuhan, China, for “three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.”

The patent application was filed on November 20, 2019 (16/689,513).

3D memory with support structures in slit structures
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,094,712) developed by Huo, Zongliang, Yang, Haohao, Xu, Wei, Yan, Ping, Huang, Pan, and Zhou, Wenbin, Wuhan, China, for “three-dimensional memory device with support structures in slit structures and method for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.”

The patent application was filed on October 31, 2019 (16/670,579).

3D NAND memory and method of forming
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,088,166) developed by Oh, Jin Yong, and Kim, Youn Cheul, Wuhan, China, for “3D NAND memory device and method of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device is provided. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure. The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.”

The patent application was filed on December 12, 2019 (16/712,210).

3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,081,524) developed by Hua, Wenyu, and Wu, Linchun, Wuhan, China, for “three-dimensional memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers above the substrate. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area. The 3D memory device further includes first channel structures each extending vertically through the first area of the memory stack and including a drain at its upper end, and second channel structures each extending vertically through the second area of the memory stack and including a source at its upper end. The 3D memory device further includes semiconductor connections disposed vertically between the substrate and the memory stack. Each semiconductor connection crosses the slit structure in a plan view to electrically connect a respective pair of first and second channel structures.”

The patent application was filed on August 15, 2019 (16/542,266).

3D memory and fabrication
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,081,496) developed by Xiao, Li Hong, Wuhan, China, for “three-dimensional memory devices and fabrication methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.”

The patent application was filed on August 14, 2019 (16/541,141).

Non-volatile memory and control
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,081,164) developed by Jia, Jianquan, Cui, Ying, and You, Kaikai, Wuhan, China, for “non-volatile memory device and control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.”

The patent application was filed on December 11, 2019 (16/709,944).

3D memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,069,712) developed by Yao, Lan, and Xue, Lei, Wuhan, China, for a “three-dimensional memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional (3D) memory device is provided. The 3D memory device includes a substrate, an alternating conductive/dielectric stack, an epitaxial layer, and a vertical structure. The alternating conductive/dielectric stack is disposed on the substrate. The alternating conductive/dielectric stack includes a plurality of dielectric layers and a plurality of conductive layers alternately stacked in a vertical direction perpendicular to a surface of the substrate. The epitaxial layer is disposed between the substrate and the alternating conductive/dielectric stack in the vertical direction. The vertical structure penetrates the alternating conductive/dielectric stack in the vertical direction for being partly disposed in the epitaxial layer. The epitaxial layer includes a protruding part disposed between the vertical structure and a bottom dielectric layer of the alternating conductive/dielectric stack in a horizontal direction orthogonal to the vertical direction.”

The patent application was filed on July 22, 2020 (16/935,223).

3D memory and fabricating methods
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,069,705) developed by Zhang, Zhong, Hua, Wenyu, and Xia, Zhiliang, Hubei, China, for “three-dimensional memory devices and fabricating methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure provides a three-dimensional (3D) memory device and a method for forming the same. The 3D memory device can comprise a channel structure region including a plurality of channel structures, a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.”

The patent application was filed on July 1, 2019 (16/458,401).

Spacial arrangments of and critical dimensions for bit line contacts of 3D phase-change memory
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,063,215) developed by Liu, Jun, Wuhan, China, for “spacial arrangments of and critical dimensions for bit line contacts of three-dimensional phase-change memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional (3D) memory device includes parallel lower and upper bit lines, parallel word lines, lower and upper memory cells, a lower bit line contact in contact with the lower bit line, and an upper bit line contact in contact with the upper bit line. The parallel word lines are in a same plane between the lower and the upper bit lines. Each word line is perpendicular to the lower and upper bit lines. Each lower memory cell is disposed at an intersection of the lower bit line and a respective word line. Each upper memory cell is disposed at an intersection of the upper bit line and a respective word line. Each lower or upper memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. At least one of the lower and upper bit line contacts is disposed inclusively between the lower and upper memory cells in a plan view.”

The patent application was filed on December 26, 2019 (16/727,852).

Non-volatile memory and manufacturing
Yangtze Memory Technologies Co., Ltd., Wuhan, China, has been assigned a patent (11,063,056) developed by Oh, Jin Yong, Wuhan, China, for “non-volatile memory device and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory device includes a first substrate, a second substrate, a memory array, a circuit structure, a bonding structure, and a shielding structure. A second front side of the second substrate faces a first front side of the first substrate. The memory array is disposed on the first substrate and disposed at the first front side of the first substrate. The circuit structure is disposed on the second substrate and disposed at the second front side of the second substrate. The bonding structure is disposed between the memory array and the circuit structure. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure is disposed between the memory array and the circuit structure and surrounds the bonding structure. The shielding structure is electrically connected to a voltage source.”

The patent application was filed on November 4, 2019 (16/672,527).