eMemory Technology Assigned Nine Patents

Memory cell and memory cell array of magnetoresistive random access memory operated by negative voltage
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,108,395) developed by Chang, Chia-Fu, Hsinchu County, Taiwan, for a “memory cell and memory cell array of magnetoresistive random access memory operated by negative voltage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.”

The patent application was filed on March 18, 2020 (16/822,983).

Non-volatile memory
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,074,963) developed by Huang, Yu-Ping, Lin, Chun-Hung, and Huang, Cheng-Da, Hsinchu County, Taiwan, for a “non-volatile memory and memory sector thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory includes a memory cell array, an amplifying circuit and a first multiplexer. The memory cell array includes m.times.n memory cells. The memory cell array is connected with a control line, m word lines and n local bit lines, wherein m and n are positive integers. The amplifying circuit includes n sensing elements. The n sensing elements are respectively connected between the n local bit lines and n read bit lines. The first multiplexer is connected with the n local bit lines and the n read bit lines. According to a first select signal, the first multiplexer selects one of the n local bit lines to be connected with a first main bit line and selects one of the n read bit lines to be connected with a first main read bit line.”

The patent application was filed on April 1, 2020 (16/837,623).

Multi-cell per bit nonvolatile memory unit
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,063,772) developed by Chen, Chih-Hsin, Changhua County, Taiwan, Lai, Tsung-Mu, Hsinchu County, Taiwan, and Wang, Shih-Chen, Taipei, Taiwan, for a “multi-cell per bit nonvolatile memory unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.”

The patent application was filed on June 6, 2018 (16/001,933).

Storage cell using charge-trapping devices
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,055,235) developed by Sun, Wein-Town, and Hsu, Ching-Hsiang, Hsinchu County, Taiwan, for a “storage cell using charge-trapping devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage cell includes a selection circuit, a first memory transistor, and a second memory transistor. The selection circuit is coupled to a source line and a common node. When the selection circuit is turned on, the selection circuit forms an electrical connection between the source line and the common node. The first memory transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a control terminal coupled to a control line. The second memory transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a control terminal coupled to the control line. The first memory transistor and the second memory transistor are 2-dimension charge-trapping devices or 3-dimension charge-trapping devices.”

The patent application was filed on December 5, 2019 (16/703,892).

Erasable programmable non-volatile memory
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,049,564) developed by Sun, Wein-Town, Chen, Hsueh-Wei, Li, Chun-Hsiao, Chen, Wei-Ren, and Liao, Hong-Yi, Hsinchu County, Taiwan, for an “erasable programmable non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.”

The patent application was filed on February 27, 2020 (16/803,585).

Memory system with random bit block
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,031,779) developed by Sun, Wein-Town, Hsinchu County, Taiwan, for a “memory system with a random bit block.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a non-volatile memory block, a random bit block, and a sense amplifier. The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data. Each of the non-volatile memory cells includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each of the random bit cells includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of a non-volatile memory cell during a read operation of the non-volatile memory cell and senses a second read current of a random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor, and the third storage transistor are storage transistors of the same type.”

The patent application was filed on April 14, 2020 (16/848,808).

Multi-time programming memory cell and memory cell array with erase inhibit capability
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,017,862) developed by Chen, Chih-Hsin, Hsinchu County, Taiwan, for “multi-time programming memory cell and memory cell array with erase inhibit capability.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.”

The patent application was filed on October 23, 2019 (16/661,603).

Memory structure, programing and reading
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,011,533) developed by Hsu, Chia-Jung, and Sun, Wein-Town, Hsinchu County, Taiwan, for “memory structure and programing and reading methods thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.”

The patent application was filed on December 14, 2018 (16/219,963).

Operating non-volatile memory cell
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11,004,505) developed by Lin, Yih-Lang, Hsinchu County, Taiwan, for a “method for operating a non-volatile memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.”

The patent application was filed on December 27, 2020 (17/134,471).