Toshiba Memory/Kioxia Assigned Twenty-Five Patents

Media error reporting improvements for storage drives
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,049,581) developed by Buxton, Neil, Berkshire, Great Britain, Asano, Shigehiro, Tokyo, Japan, Wells, Steven, Rancho Cordova, CA, and Carlson, Mark, Longmont, CO, for a “media error reporting improvements for storage drives.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.”

The patent application was filed on March 6, 2020 (16/811,694).

Memory and controlling nonvolatile memory
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,042,487) developed by Yoshida, Hideki, Yokohama Kanagawa, Japan, and Kanno, Shinichi, Tokyo, Japan, for “memory system and method for controlling nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.”

The patent application was filed on August 29, 2019 (16/555,663).

Data storage resource management
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,042,411) developed by Klein, Yaron, Raanana, Israel, for a “data storage resource management.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A resource management system in a data center one or more data storage resource providers and a transaction server. The transaction server is configured to receive, from a client, a request for read and/or write access for a data storage resource, the request comprising one or more specifications, to provide, to the one or more data storage resource providers, at least a portion of the request, and to receive, from the one or more data storage resource providers, respective responses to the request, the responses respectively comprising one or more allocation options. The transaction server is further configured to select one of the one or more allocation options for registration, and register the selected allocation option with a data manager. At least one of the one or more data storage providers is configured to provide the data storage resource in accordance with the registered allocation option.”

The patent application was filed on March 15, 2019 (16/355,588).

Command load balancing for NVME dual port operations
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,042,300) developed by Olcay, Sancar Kunt, Sunnyvale, CA, and Lai, Dishi, San Jose, CA, for a “command load balancing for NVME dual port operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.”

The patent application was filed on March 31, 2015 (14/674,632).

Semiconductor storage and manufacturing
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,037,948) developed by Matsushita, Sonoe, Mie, Japan, Nishimura, Takahito, Yoshimochi, Kazuyuki, Kuwana, Japan, Yanai, Yoshihiro, Yokkaichi, Japan, and Usui, Satoshi, Nagoya, Japan, for “semiconductor storage device and method for manufacturing semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells, and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.”

The patent application was filed on September 5, 2019 (16/561,521).

Semiconductor storage device having group adjacent bit lines connected to sense circuits that are each connected to different data bus
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,037,634) developed by Komai, Hiromitsu, Kamakura Kanagawa, Japan, for a “semiconductor storage device having a group adjacent bit lines connected to sense circuits that are each connected to a different data bus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.”

The patent application was filed on February 21, 2018 (15/901,881).

Storage having host directly manage physical data locations of storage device
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,036,628) developed by Hashimoto, Daisuke, Cupertino, CA, for a “storage system having a host directly manage physical data locations of storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.”

The patent application was filed on September 30, 2019 (16/588,438).

Semiconductor storage and manufacturing
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,031,416) developed by Miyazaki, Maki, Yokkaichi, Japan, for “semiconductor storage device and method for manufacturing semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a semiconductor storage device includes: a first stacked body in which a plurality of conductive layers are stacked via a first insulating layer, the first stacked body having a first stepped portion and a second stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in a lower layer, a second stacked body in which a plurality of second insulating layers are stacked via a third insulating layer, the second stacked body having a third stepped portion in which end portions of the plurality of second insulating layers in an identical level as the conductive layers forming the first stepped portion are formed in a step shape. The first stepped portion and the third stepped portion oppose each other, and the second stepped portion and the third stepped portion overlap each other at least partially in a top view.”

The patent application was filed on September 9, 2019 (16/564,381).

Semiconductor storage device
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,031,415) developed by Minemura, Yoichi, Yokkaichi, Japan, Matsuo, Michiaki, and Shamoto, Reiko, Nagoya, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.”

The patent application was filed on September 4, 2019 (16/560,416).

Semiconductor storage and control method with detecting levels of multi-ary signal
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,024,375) developed by Sugimoto, Takeshi, Yokohama, Japan, for “semiconductor storage device and control method of semiconductor storage device with detecting levels of a multi-ary signal.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.”

The patent application was filed on November 29, 2017 (15/825,699).

Storage device and control
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,023,136) developed by Higashi, Hirotaka, Kawasaki Kanagawa, Japan, for “storage device and control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a non-volatile memory including a buffer of a first size and a controller. The controller is configured to transmit a control command to the non-volatile memory, and then repeat a process including a first process of changing a phase value of a timing signal indicating timing to read or write data from or to the non-volatile memory and a second process of reading or writing data having a second size smaller than the first size from or to the non-volatile memory in synchronization with the timing signal of the changed phase value, a certain plurality of times without transmitting any other control command to the non-volatile memory during repetition of the process.”

The patent application was filed on February 28, 2019 (16/289,339).

Semiconductor device and manufacturing
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,018,217) developed by Ishida, Takashi, Sugimoto, Takahiro, Kanno, Hiroshi, and Okamoto, Tatsuya, Mie, Japan, for “semiconductor device and method for manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.”

The patent application was filed on August 23, 2019 (16/549,826).

Storage device having memory cell with variable resistance element
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,017,854) developed by Suzuki, Kunifumi, Yokkaichi Mie, Japan, for a “storage device having a memory cell with a variable resistance element, in which voltage applied to a word line of the memory cell is controlled based on voltage of a bit line of the memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a first layer extending in a first direction, a second layer extending in a second direction intersecting the first direction, a third layer extending in a third direction intersecting the first and second directions, a first transistor including a first gate electrode electrically connected to the second layer, a first selection transistor having a first end electrically connected to the third layer and a second end electrically connected to the second layer, a first cell including a first element electrically connected between the first and second layers and to a node of the second layer that is between the first gate electrode of the first transistor and the second end of the first selection transistor, and a circuit turning on the first selection transistor to electrically connect the first cell to the third layer during a write operation performed on the first cell.”

The patent application was filed on September 3, 2019 (16/558,905).

Error correction code structure
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,016,844) developed by Steiner, Avi, Kiriat Motzkin, Israel, Weingarten, Hanan, Herzliya, Israel, Nadam-Olegnowicz, Meir, Binyamina, Israel, Kanter, Ofir, and Nassie, Amir, Haifa, Israel, for an “error correction code structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.”

The patent application was filed on March 15, 2019 (16/355,559).

Semiconductor storage
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,011,225) developed by Matsunami, Junya, Yokkaichi Mie, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a semiconductor storage device includes a first wiring, a first resistance change element which is connected to the first wiring, a first nonlinear element which is connected to the first resistance change element, and a second wiring which is connected to the first nonlinear element. In a read operation for the first resistance change element, a voltage between the first wiring and the second wiring increases to a first voltage, and after the voltage between the first wiring and the second wiring increases to the first voltage, the voltage between the first wiring and the second wiring increases to a second voltage which is larger than the first voltage.”

The patent application was filed on September 4, 2019 (16/560,584).

Semiconductor storage
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,006,526) developed by Kumagai, Kengo, Yokohama, Japan, Tanuma, Daigo, Kunitachi, Japan, and Mizuno, Masahiro, Yokohama, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a semiconductor storage device includes a board, a semiconductor memory component, and a capacitor. The hoard includes a first pad and a second pad. The first capacitor includes a first electrode and a second electrode. The first pad includes a first region and a second region. A direction from the first pad to the second pad is a first direction and a direction different from the first direction is a second direction. A difference between a dimension of the second region in the second direction and a dimension of the first electrode in the second direction is smaller than a difference between a dimension of the first region in the second direction and a dimension of the first electrode in the second direction.”

The patent application was filed on March 8, 2019 (16/297,182).

Reconfigurable SSD storage pool
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (11,003,376) developed by Xiao, Edward, Alameda, CA, and Stetzer, Scott, Foothill Ranch, CA, for a “reconfigurable SSD storage pool.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.”

The patent application was filed on September 13, 2019 (16/570,455).

Memory
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,997,049) developed by Hiruta, Tatsuro, Yokohama, Japan, for a “memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes a memory device including first storage elements which store data, a temperature sensor which measures a temperature of the memory device, and a controller including a processor which acquires a current temperature from the temperature sensor as a first temperature, acquires a temperature when the data is written into the first storage element, from the memory device as a second temperature, determines whether a difference between the first temperature and the second temperature exceeds a predetermined temperature difference, and when the difference exceeds the predetermined temperature difference, instructs the memory device to rewrite the data written in the first storage element. The memory device includes a sequencer which determines a voltage for the rewrite, based on the difference and a voltage when the data is written into the first storage element.”

The patent application was filed on September 10, 2019 (16/566,277).

Deterministic read disturb counter-based data checking for NAND flash
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,996,870) developed by Buxton, Neil, Berkshire, Great Britain, for a “deterministic read disturb counter-based data checking for NAND flash.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.”

The patent application was filed on March 6, 2020 (16/811,775).

Semiconductor storage and controlling
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,991,402) developed by Sugahara, Akio, Yokohama, Japan, Harada, Yoshikazu, and Hashimoto, Shoichiro, Kawasaki, Japan, for “semiconductor storage device and method of controlling the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.”

The patent application was filed on April 2, 2020 (16/838,091).

Nonvolatile storage
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,985,210) developed by Nakayama, Masahiko, Nagase, Toshihiko, Kuwana Mie, Japan, Funayama, Tomomi, Mie Mie, Japan, Furuhashi, Hironobu, Kuwana Mie, Japan, and Sunouchi, Kazumasa, Yokohama Kanagawa, Japan, for a “nonvolatile storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.”

The patent application was filed on September 3, 2019 (16/559,254).

Nonvolatile storage
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,985,209) developed by Nakayama, Masahiko, Kuwana Mie, Japan, Sunouchi, Kazumasa, Yokohama Kanagawa, Japan, Sudo, Gaku, Yokkaichi Mie, Japan, and Kai, Tadashi, Yokohama Kanagawa, Japan, for a “nonvolatile storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.”

The patent application was filed on September 3, 2019 (16/559,162).

Semiconductor memory and manufacturing
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,985,178) developed by Kashima, Takayuki, Yokkaichi Mie, Japan, for “semiconductor memory device and method of manufacturing semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a semiconductor memory device includes a plurality of first conductor layers stacked in a first direction, a second conductor layer provided above the first conductor layer, a first semiconductor layer extending in the first direction in the plurality of first conductor layers, a second semiconductor layer including a first portion extending in the first direction in the second conductor layer and a second portion of which a diameter in a cross section orthogonal to the first direction is larger than a diameter of the first portion, and being in contact with the first semiconductor layer in the second portion, and a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer. An upper end of the first charge storage layer protrudes upward in the first direction in comparison with an upper end of the first semiconductor layer.”

The patent application was filed on August 2, 2019 (16/530,564).

Non-volatile storage and manufacturing
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,985,173) developed by Higuchi, Masaaki, Yokkaichi Mie, Japan, Kito, Masaru, Kuwana Mie, Japan, and Shingu, Masao, Yokkaichi Mie, Japan, for “non-volatile storage device and method of manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.”

The patent application was filed on February 15, 2018 (15/897,623).

Memory that constructs virtual storage regions for virtual machines
Toshiba Memory Corporation, now Kioxia Corporation, Tokyo, Japan, has been assigned a patent (10,983,701) developed by Kanno, Shinichi, Tokyo, Japan, for a “memory system that constructs virtual storage regions for virtual machines.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.”

The patent application was filed on August 29, 2017 (15/690,188).