Kioxia Assigned Seventeen Patents

Memory card with multiple modes, and host device corresponding to memory card
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,093,811) developed by Fujimoto, Akihisa, Yamato, Japan, Saito, Toshitada, Yokohama, Japan, Sakamoto, Noriya, Chigasaki, Japan, and Kondo, Atsushi, Yokohama, Japan, for “memory card with multiple modes, and host device corresponding to the memory card.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory card includes a first surface, a second surface, and 1.sup.st to N.sup.th terminal groups. The first surface includes first to N.sup.th rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1.sup.st to N.sup.th terminal groups are placed in the first to N.sup.th rows. The 1.sup.st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. K.sup.th terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.”

The patent application was filed on March 9, 2018 (16/619,012).

Memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,093,173) developed by Yamaki, Ryo, Park, Gibeom, Ng, Youyang, Horisaki, Koji, and Horiuchi, Kazuhisa, Yokohama, Japan, for a “memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.”

The patent application was filed on February 14, 2020 (16/790,807).

Efficiently store object data of object storage service on magnetic disk drive and magnetic SMR disk drive
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,093,149) developed by Gole, Abhijeet, Cupertino, CA, Joshi, Ratnadeep, Sunnyvale, CA, and Kufeldt, Philip A., San Jose, CA, for a “method to efficiently store object data of an object storage service on a magnetic disk drive and magnetic SMR disk drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In a data storage system, the available space of a magnetic storage device is divided into multiple sequential write regions for storing sequentially written data, where the regions are each separated from adjacent sequential write regions by a guard space. Object data, such as key-value pairs, are written sequentially to a particular sequential write region, in blocks of data that correspond to the contents of a nonvolatile buffer being flushed to the magnetic storage device. When a key-value pair stored in the magnetic storage device is subsequently updated, the original key-value pair is not overwritten. Instead, the new version of the key-value pair is included in the next block of data to be written to the magnetic storage device, and a mapping table tracks the location of the newest version of each key-value pair stored in the magnetic storage device.”

The patent application was filed on October 17, 2019 (16/656,350).

Memory system
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,086,718) developed by Suzuki, Riki, Hida, Toshikatsu, Yokohama Kanagawa, Japan, Kojima, Yoshihisa, Kawasaki Kanagawa, Japan, Amaki, Takehiko, Yokohama Kanagawa, Japan, and Nishikawa, Suguru, Osaka Osaka, Japan, for a “memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory, write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits, and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.”

The patent application was filed on March 2, 2020 (16/806,131).

Decoding scheme for error correction code structure in storage devices
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,082,069) developed by Steiner, Avi, Kiriat Motzkin, Israel, and Weingarten, Hanan, Herzliya, Israel, for “decoding scheme for error correction code structure in data storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.”

The patent application was filed on April 8, 2020 (16/843,774).

Nonvolatile memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,081,526) developed by Yamamoto, Kazuhiko, Fujisawa Kanagawa, Japan, for a “nonvolatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a nonvolatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a third wiring extending in the second direction and spaced from the second wiring in the first direction. An insulating layer includes a first portion between the second wiring and the third wiring, and a second portion protruding from the first portion in a third direction. A chalcogenide layer is between the first wiring and the second wiring, the first wiring and the third wiring, and also the first wiring and the insulating layer. The chalcogenide layer includes a first layer portion, a second layer portion, and a third layer portion. A concentration of a first element in the third layer portion is higher than that in the first and second layer portions.”

The patent application was filed on February 27, 2020 (16/803,863).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,081,188) developed by Yanagidaira, Kosuke, Fujisawa Kanagawa, Japan, and Tsubouchi, Hiroshi, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.”

The patent application was filed on January 28, 2020 (16/774,630).

Memory system and control of memory system for controlling of first and second writing operations
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,081,183) developed by Ogawa, Masahiro, Odawara, Japan, and Aoyama, Norio, Machida, Japan, for “memory system and control method of memory system for controlling of first and second writing operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a memory system includes a semiconductor memory device including a first and second string each including cells coupled in series, and a memory controller configured to instruct the device to execute a write operation for writing data on any one of the cells in the first or second string. The first and second string are coupled in parallel between a bit line and a source line, and coupled to different word lines. The write operation includes a first write operation and a second write operation executed after the first write operation. The controller is configured to instruct the device to execute a first write operation on a second cell in the second string between a first write operation on a first cell in the first string and a second write operation on the first cell.”

The patent application was filed on March 11, 2020 (16/815,073).

Semiconductor device and memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,081,175) developed by Niki, Yusuke, Yokohama Kanagawa, Japan, Kawasumi, Atsushi, Fujisawa Kanagawa, Japan, and Miyazaki, Takayuki, Tokyo, Japan, for “semiconductor device and memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a device includes first lines transmitting a first signals, second lines receiving the first signals, and a first circuit including a first selector coupled to the first lines, a second selector coupled to the second lines, third lines and a fourth lines between the first and second selectors. Each of the third lines stores the second signals, each of the fourth lines stores the third signals. The first circuit counts a first number of second signals equivalent to the corresponding first signal, counts a second number of third signals equivalent to corresponding first signal of the first signals, and couples either the third or the fourth lines to the first and second lines via the first and second selectors, based on a result of comparison between the first and the second numbers.”

The patent application was filed on July 30, 2020 (16/943,638).

Information processing apparatus/system, and semiconductor storage
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,081,163) developed by Fujimoto, Akihisa, Yamato, Japan, and Kondo, Atsushi, Yokohama, Japan, for “information processing apparatus, information processing system, and semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.”

The patent application was filed on March 13, 2020 (16/817,832).

Semiconductor device
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,075,220) developed by Komiya, Ken, Nagoya Aichi, Japan, for a “semiconductor device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.”

The patent application was filed on September 10, 2020 (17/016,630).

Semiconductor device and manufacturing
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,075,122) developed by Shioda, Tomonari, and Ishida, Takashi, Yokkaichi, Japan, for “semiconductor device and manufacturing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor device according to an embodiment includes: a semiconductor substrate including a first surface, a first contact part provided at a deeper level than the first surface, and a second contact part protruding up to a higher level than the first surface from the first contact part, a stacked body in which insulating layers and electrode layers are alternately stacked on the first surface, and a semiconductor film extending, on the second contact part, in the stacked body in a first direction perpendicular to the first surface. At an interface between the first contact part and the second contact part, a length of the first contact part in a second direction parallel to the first surface is larger than a length of the second contact part in the second direction.”

The patent application was filed on March 6, 2020 (16/811,065).

Memory and controlling nonvolatile memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,074,178) developed by Yamaguchi, Kensaku, Kawasaki, Japan, and Kanno, Shinichi, Ota, Japan, for “memory system and method of controlling nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.”

The patent application was filed on March 2, 2020 (16/805,946).

Memory and nonvolatile memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,069,413) developed by Nishikawa, Suguru, Osaka, Japan, Suzuki, Riki, Yokohama, Japan, and Kojima, Yoshihisa, Kawasaki, Japan, for “memory system and nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation, in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section, and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.”

The patent application was filed on February 25, 2020 (16/799,885).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,069,407) developed by Tsukamoto, Takayuki, Yokkaichi Mie, Japan, Furuhashi, Hironobu, Kuwana Mie, Japan, Sugimoto, Takeshi, Yokohama Kanagawa, Japan, and Komura, Masanori, Kuwana Mie, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor memory device includes: first wirings, second wirings intersecting the first wirings, and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.”

The patent application was filed on March 3, 2020 (16/807,850).

Semiconductor memory
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,069,405) developed by Inuzuka, Yuki, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor memory device of an embodiment has stacked semiconductor memories, each semiconductor memory including first lines intersecting with second lines, and resistive change elements each disposed between one of the first lines and one of the second lines. In two of the semiconductor memories adjacent to each other in the stacking direction, either two of the first lines or two of the second lines are disposed along and in contact with each other. A first contact electrically connected to the second line of the uppermost semiconductor memory passes through a region between the second lines of each of the semiconductor memories located below the uppermost semiconductor memory, and a second contact electrically connected to the second line of each of the semiconductor memories located at an intermediate level passes through a region between the second lines of each of the semiconductor memories located below the intermediate level.”

The patent application was filed on March 6, 2020 (16/811,209).

Memory device
Kioxia Corporation, Minato-ku, Japan, has been assigned a patent (11,062,770) developed by Inaba, Tsuneo, Kamakura Kanagawa, Japan, and Kawasumi, Atsushi, Fujisawa Kanagawa, Japan, for a “memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.”

The patent application was filed on June 24, 2020 (16/910,826).