Sony Semiconductor Solutions Assigned Two Patents

Hit-based ratio write cache operation mode in storage controller
Sony Semiconductor Solutions Corp., Kanagawa, Japan, has been assigned a patent (11,023,381) developed by Kaneda, Teruya, Kanagawa, Japan, Nakanishi, Kenichi, Tokyo, and Japan, Okubo, Hideaki, Saitama, Japan, for “system and method for a hit-based ratio write cache operation mode in a storage controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.”

The patent application was filed on February 5, 2018 (16/611,532).

Storage apparatus
Sony Semiconductor Solutions Corp., Kanagawa, Japan, has been assigned a patent (11,018,189) developed by Nonoguchi, Seiji, Aratani, Katsuhisa, Kanagawa, Japan, and Ohba, Kazuhiro, Tokyo, Japan, for a “storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.”

The patent application was filed on March 15, 2018 (16/490,303).