Ovonyx Memory Technology Assigned Four Patents

Variable resistance memory with lattice array using enclosing transistors
Ovonyx Memory Technology, LLC, LLC, Alexandria, VA, has been assigned a patent (11,062,771) developed by Liu, Jun, Boise, ID, for a “variable resistance memory with lattice array using enclosing transistors.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.”

The patent application was filed on January 29, 2020 (Appl. No.16/776,383).

Memory devices including phase change material elements
Ovonyx Memory Technology, LLC, Alexandria, VA, has been assigned a patent (11,050,019) developed by Liu, Jun, Boise, ID, for “memory devices including phase change material elements.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.”

The patent application was filed on May 15, 2019 (16/413,483).

Phase change memory switch wall cell with approximately horizontal electrode contact cross references
Ovonyx Memory Technology, LLC, Alexandria, VA, has been assigned a patent (11,031,553) developed by Pellizzer, Fabio, Comate D’Adda, Italy, and Tortorelli, Innocenzo, Moncalieri, Italy, for “method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.”

The patent application was filed on January 29, 2020 (16/776,391).

Memory cell and memory cell array
Ovonyx Memory Technology, LLC, Alexandria, VA, has been assigned a patent (11,031,069) developed by Okhonin, Serguei, St-Sulpice, Switzerland, and Nagoga, Mikhail, Lausanne, Switzerland, for “memory cell and memory cell array having an electrically floating body transistor, and methods of operating same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.”

The patent application was filed on September 13, 2019 (16/570,634).