Taiwan Semiconductor Manufacturing Assigned Sixteen Patents

Phase change memory structure to reduce power consumption
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,463) developed by Tsai, Yi Jen, New Taipei, Taiwan, and Liu, Shih-Chang, Alian Township, Taiwan, for a “phase change memory structure to reduce power consumption.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell.”

The patent application was filed on October 2, 2019 (16/590,587).

Memory device
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,458) developed by Peng, Tai-Yen, Hsinchu, Taiwan, Wei, Hui-Hsien, Taoyuan, Taiwan, Wen, Wei-Chih, Hsinchu County, Taiwan, Dai, Pin-Ren, New Taipei, Taiwan, Lee, Chien-Min, Lai, Sheng-Chih, Hsinchu County, Taiwan, Tsai, Han-Ting, Kaohsiung, Taiwan, and Lin, Chung-Te, Tainan, Taiwan, for a “memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.”

The patent application was filed on May 4, 2020 (16/866,106).

Fabricating magneto-resistive random-access memory (MRAM)
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,455) developed by Tien, Hsi-Wen, Xinfeng Township, Hsinchu County, Taiwan, Liao, Wei-Hao, Taichung, Taiwan, Dai, Pin-Ren, New Taipei, Taiwan, Lu, Chih-Wei, and Lee, Chung-Ju, Hsinchu, Taiwan, Taiwan, for “methods of fabricating magneto-resistive random-access memory (MRAM) devices to avoid damaging magnetic tunnel junction (MTJ) structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.”

The patent application was filed on September 6, 2018 (16/123,034).

Making semiconductor device comprising flash memory
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,380) developed by Lin, Chien-Hung, Hsin-Chu, Taiwan, Mo, Chun-Chieh, Kaohsiung, Taiwan, and Kuo, Shih-Chi, Yangmei, Taiwan, for “method of making semiconductor device comprising flash memory and resulting device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer, forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material, etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer, and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.”

The patent application was filed on April 29, 2020 (16/861,668).

Magnetic device and magnetic random access memory
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,307) developed by Tsai, Wilman, Saratoga, CA, Lin, Shy-Jay, Jhudong Township, Taiwan, and Song, Mingyuan, Hsinchu, Taiwan, for “magnetic device and magnetic random access memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. A diffusion barrier layer for suppressing metal elements of the first magnetic layer from diffusing into the bottom metal layer is disposed between the bottom metal layer and the first magnetic layer.”

The patent application was filed on May 30, 2019 (16/427,308).

Embedded non-volatile memory with side word line
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,181) developed by Tu, Yung-Chun, Kaohsiung, Taiwan, Yang, Tsung-Yu, Tainan, Taiwan, and Huang, Chung-Jen, Tainan, Taiwan, for an “embedded non-volatile memory with side word line.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes a semiconductor substrate, a control gate, a word line, a dielectric layer, a charge storage nitride layer, and a blocking layer. The semiconductor substrate has a source region and a drain region. The control gate and a word line are disposed over the semiconductor substrate and located between the source and drain regions. The dielectric layer is in contact with the semiconductor substrate and disposed between the semiconductor substrate, the control gate, and the word line. The charge storage nitride layer is disposed between the dielectric layer and the control gate. The blocking layer is disposed between the charge storage nitride layer and the control gate.”

The patent application was filed on February 9, 2017 (15/428,260).

Humidity control in storage device
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,879,099) developed by Yang, Sheng-Chun, Lin, Yi-Ming, Tainan, Taiwan, Wan, Chao-Hung, Hsu, Hsiu Hao, Chen, Guan Jung, and Liang, Po-Wei, Hsinchu, Taiwan, for a “humidity control in storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A humidity-controlled storage device includes a plurality of panels configured to form an enclosed volume. A first panel of the plurality of panels includes inlet and outlet ports. The storage device further includes a purge system with a gas inlet pipe, a gas supply system, and a gas extraction system. The gas inlet pipe includes a nozzle and a cylindrical portion coupled to the inlet port. The gas supply system is configured to supply a purge gas to the gas inlet pipe. The gas inlet pipe is configured to output the purge gas into the enclosed volume in a direction that creates a circular or an oval gas flow pattern within the enclosed volume. The gas extraction system is coupled to the outlet port and is configured to extract the purge gas from the enclosed volume.”

The patent application was filed on January 2, 2019 (16/238,001).

Layout structure of memory array
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,878,930) developed by Chang, Meng-Sheng, Yang, Yao-Jen, Chou, Shao-Yu, Hsinchu County, Taiwan, and Wang, Yih, Hsinchu, Taiwan, for a “layout structure of memory array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells, disposing a word line between the first row and the second row, disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively, disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line, and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line, wherein the first side of the word line is opposite to the second side of the word line.”

The patent application was filed on July 12, 2019 (16/509,524).

Latch-up prevention circuit for memory storage
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,878,852) developed by Lin, Sungchieh, Zhubei, Taiwan, and Hsu, Kuoyuan, Peter, San Jose, CA, for a “latch-up prevention circuit for memory storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storage systems selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storage systems selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption. Moreover, the configurable memory storage systems selectively provide the maximum operational voltage signal to bulk (B) terminals of some of their transistors to prevent latch-up of these transistors. In some situations, the configurable memory storage systems can dynamically adjust the maximum operational voltage signal to compensate for fluctuations in the maximum operational voltage signal.”

The patent application was filed on November 2, 2018 (16/179,332).

Storage device having magnetic tunnel junction cells of different sizes
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,868,234) developed by Chuang, Harry-Hak-Lay, Hsinchu County, Taiwan, Chen, Chang-Hung, Shen, Kuei-Hung, Hsinchu, Taiwan, You, Wen-Chun, Yilan County, Taiwan, and Chiang, Tien-Wei, Taipei, Taiwan, for “storage device having magnetic tunnel junction cells of different sizes, and method of forming storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage device includes: a plurality of first magnetic tunnel junction (MTJ) cells disposed on a first portion of a substrate, and a plurality of second MTJ cells disposed on a second portion different from the first portion of the substrate, wherein each of the plurality of first MTJ cells has a first cross-sectional surface area viewing from a top of the substrate, each of the plurality of second MTJ cells has a second cross-sectional surface area viewing from the top of the substrate, and the second cross-sectional surface area is greater than the first cross-sectional surface area.”

The patent application was filed on December 12, 2018 (16/217,681).

Memory device
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,854,618) developed by Liu, Chien Hung, Hsinchu County, Taiwan, for “memory device and method of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes: a conductive layer coupled to a reference voltage level, a first storage portion vertically coupled to a first surface of the conductive layer, and a second storage portion vertically coupled to a second surface of the conductive layer, wherein the second surface is opposite to the first surface.”

The patent application was filed on September 28, 2017 (15/719,466).

Memory device with enhanced access capability
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,854,283) developed by Lu, Shih-Lien Linus, Hsinchu, Taiwan, for “memory device with enhanced access capability and associated method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation. The memory array further includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.”

The patent application was filed on November 20, 2019 (16/689,852).

Switching layer scheme to enhance RRAM performance
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,811,600) developed by Trinh, Hai-Dang, Hsinchu, Taiwan, Tsai, Cheng-Yuan, Chu-Pei, Taiwan, Lin, Hsing-Lien, Hsin-Chu, Taiwan, and Chu, Wen-Ting, Kaohsiung, Taiwan, for a “switching layer scheme to enhance RRAM performance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure has a plurality of sub-layers including one or more metals having non-zero concentrations that change as a distance from the first electrode increases.”

The patent application was filed on October 17, 2019 (16/655,478).

Leakage pathway prevention in memory storage
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,762,934) developed by Wu, Shang-Chi, Lee, Cheng Hung, Hsinchu, Taiwan, Su, Chien-Kuo, Kaohsiung County, Taiwan, Cheng, Chiting, Taichung, Taiwan, Hsu, Yu-Hao, Tainan, Taiwan, and Lin, Yangsyu, New Taipei, Taiwan, for a “leakage pathway prevention in a memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.”

The patent application was filed on January 31, 2019 (16/263,904).

Failure detection circuitry for address decoder for storage device
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,706,934) developed by Fujiwara, Hidehiro, Hsinchu, Taiwan, and Wu, Ching-Wei, Nantou County, Taiwan, for a “failure detection circuitry for address decoder for a data storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.”

The patent application was filed on July 12, 2019 (16/510,168).

RRAM cell structure with laterally offset BEVA/TEVA
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (10,700,275) developed by Chang, Chih-Yang, Yuanlin Township, Taiwan, Chu, Wen-Ting, Kaohsiung, Taiwan, Tu, Kuo-Chi, Hsin-Chu, Taiwan, Liao, Yu-Wen, New Taipei, Taiwan, Chen, Hsia-Wei, Taipei, Taiwan, Yang, Chin-Chieh, New Taipei, Taiwan, Shih, Sheng-Hung, Hsinchu, Taiwan, and You, Wen-Chun, Dongshan Township, Taiwan, for a “RRAM cell structure with laterally offset BEVA/TEVA.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.”

The patent application was filed on December 20, 2018 (16/227,096).