R&D: Integration of Fluorographene Trapping Medium in MoS2-Based Non Volatile Memory Device

Journal of Applied Physics has published an article written by Kai Ping Chang, Department of Electronic Engineering, Chang Gung University, Guishan Dist., Taoyuan 33302, Taiwan, Haneen Abushammala,IMPMC, Sorbonne Université, CNRS, MNHN, 4, place Jussieu, 75005 Paris, France, Mamina Sahoo, Department of Electronic Engineering, Chang Gung University, Guishan Dist., Taoyuan 33302, Taiwan, Alexandre Jaffre, David Alamarguy, Université Paris-Saclay, CentraleSupélec, CNRS, Laboratoire de Génie Electrique et Electronique de Paris, 91192 Gif-sur-Yvette, France, Sorbonne Université, CNRS, Laboratoire de Génie Electrique et Electronique de Paris, 75252 Paris, France, and Yu Jiang, CINTRA UMI CNRS/NTU/THALES 3288, Research Techno Plaza, 50 Nanyang Drive, Border X Block, Level 6, Singapore 637553, Mohamed Boutchich,Université Paris-Saclay, CentraleSupélec, CNRS, Laboratoire de Génie Electrique et Electronique de Paris, 91192 Gif-sur-Yvette, France, Sorbonne Université, CNRS, Laboratoire de Génie Electrique et Electronique de Paris, 75252 Paris, France, and CINTRA UMI CNRS/NTU/THALES 3288, Research Techno Plaza, 50 Nanyang Drive, Border X Block, Level 6, Singapore 637553, and Chao-Sung Lai1,Department of Nephrology, Chang Gung Memorial Hospital, Linkou, Taoyuan 33305, Taiwan, and Department of Materials Engineering, Ming Chi University of Technology, New Taipei City 24301, Taiwan.

Abstract: “Graphene and 2D analogs such as transition metal dichalcogenides (TMDCs) have been widely investigated for their tuneable electronic properties. There is a large spectrum of applications of such 2D analogs; for example, non-volatile memory, which is a key building block for future low-power consumer electronics. In this work, we have investigated a vertical heterostructure composed of a chemical vapour-deposited molybdenum disulphide transistor channel coupled with silicon tunnel oxide (SiO₂) and hafnium oxide as a blocking barrier, with fluorographene (FGr) being used as the charge trapping medium. Owing to the larger trap density of FGr, the memory window is three times larger, and the data retention measurements at room temperature yield a 50% charge loss extrapolated to 10 years. The low barrier at the Fgr/SiO₂ interface induces a steeper charge loss for holes. Nevertheless, the stack can sustain at least to 550 cycles without showing any sign of degradation. Although bandgap engineering is required to improve the data retention, particularly for the holes, the combination studied here is an encouraging route for 2D-based non-volatile memories.“