R&D: NMTSim Transaction-Command Based Simulator for New Memory Technology Devices

IEEE Computer Architecture Letters has published an article written by Peng Gu, Electrical Computer Engineering, University of California Santa Barbara, 8786 Santa Barbara, California USA 93106-9010, Benjamin Lim, Samsung Semiconductor Inc USA, 497541 San Jose, California USA, Wenqin Huangfu, University of California Santa Barbara, 8786 Santa Barbara, USA, Krishna Malladi, Andrew Chang, Samsung Semiconductor Inc USA, 497541 San Jose, California, USA, and Yuan Xie, Electrical and Computer Engineering, University of California Santa Barbara, 8786 Santa Barbara, California, USA.

Abstract: “To mitigate the impact of non-deterministic media access latencies in new memory technology devices, a recently proposed NVDIMM (Non-Volatile Dual In-line Memory Module) standard, NVDIMM-P, uses novel out-of-order transaction commands. The previous DRAM simulators are unable to support this transaction protocol due to deterministic DDR timing. Also, existing NVDIMM simulators are customized for NAND flash memory, which are not generally applicable to emerging NVM (Non-Volatile Memory). In this paper, we present NMTSim, a transaction-command based and cycle accurate simulator for new memory technology devices. Strictly conforming with NVDIMM-P standard, NMTSim introduces a new memory controller with transaction handling and command issuing logic. To enable simulation for emerging NVM using DDR4 standard, we propose some new NVM timing parameters and incorporated them into DRAMSim2. Furthermore, DRAMSim2 is augmented with transaction handling and command scheduling logic to be the backend for the media controller. In addition, NMTSim incorporates an optimized transaction command issuing policy and an early notification mode to optimize access latency. We verify NMTSim using Intel Optane memory, and characterize its performance using synthetic benchmarks with different read/write ratio.“