ScaleFlux Assigned Two Patents

I/O performance enhancement of solid-state data storage
ScaleFlux, Inc., San Jose, CA, has been assigned a patent (10,564,895) developed by Wu, Qi, San Jose, CA, Nguyen, Duy, Fremont, CA, Amritkar, Prathamesh, and Li, Qing, San Jose, CA, for “I/O performance enhancement of solid-state data storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory, and a controller that includes: an I/O request handler for handling standard read and write, (R/W) operations requested from a host, a garbage collection, (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations, and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.”

The patent application was filed on May 11, 2018 (15/977,275).

In-memory data storage with adaptive memory fault tolerance
ScaleFlux, Inc., San Jose, CA, has been assigned a patent (10,534,664) developed by Zhang, Tong, Albany, NY, Zhong, Hao, Los Gatos, CA, Sun, Fei, Irvine, CA, and Liu Yang, Milpitas, CA, for an “in-memory data storage with adaptive memory fault tolerance.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage aware memory controller for managing a physical storage system. A described controller: a system for mapping physical memory space into a memory region and a storage region; a system for applying different error protections schemes, in which a fine-grained memory fault tolerance scheme is applied to data in the memory region and a course-grained memory fault tolerance scheme is applied to data in the storage region; and a storage file system that includes a mapping table for mapping logical addresses to physical addresses for data stored in the storage region.”

The patent application was filed on January 27, 2017 (15/417,853).