R&D: Quantitative 3D Model to Explain Large Single Trap Charge Variability in Vertical NAND Memory

Outline sampling strategy allows to reproduce experimental distributions for realistic grain size (12nm) and highlights role of transconductance to explain anomalous large shifts.

This is a Press Release edited by StorageNewsletter.com on March 20, 2020 at 2:15 pm

IEEE Xplore has published, in 2019 IEEE International Electron Devices Meeting (IEDM) proceedings, an article written by D. Verreck, A. Arreghini, J.P. Bastos, imec, Leuven, Belgium, 3001, F. Schanovsky , F. Mitterbauer, C. Kernstock, M. Karner, Global TCAD Solutions GmbH., Vienna, Austria, 1010, R. Degraeve,G. Van den bosch, and A. Furnémont, imec, Leuven, Belgium, 3001.

Abstract: “We present a TCAD model that reproduces large single trap V T -shifts (>100mV) in 3-D NAND flash read current by means of targeted charge placement based on linear response. With this model, we investigate worst-case V T -shifts in terms of bias conditions and junction position, showing low local carrier density at the origin of large shifts. We outline a sampling strategy that allows to reproduce experimental distributions for realistic grain size (12nm) and highlight the role of transconductance to explain anomalous large shifts.“