Intel Assigned Eleven Patents

Storage appliance for processing of functions as a service, (FaaS)
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,545,925) developed by Trika, Sanjeev N., Khan, Jawad B., Portland, OR, and Wysocki, Piotr, Gdansk, Poland, for a “storage appliance for processing of functions as a service,(FaaS).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data, and write data to the at least one storage device.”

The patent application was filed on June 6, 2018 (16/001,398).

Technologies for low-latency interface to data storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,542,333) developed by Miller, Steven C., Livermore, CA, for “technologies for a low-latency interface to data storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Technologies for a low-latency interface with data storage of a storage sled in a data center are disclosed. In the illustrative embodiment, a storage sled stores metadata including the location of data in a storage device in low-latency non-volatile memory. When accessing data, the storage sled may access the metadata on the low-latency non-volatile memory and then, based on the location determined by the access to the metadata, access the location of the data in the storage device. Such an approach results in only one access to the data storage in order to read the data instead of two.”

The patent application was filed on December 30, 2016 (15/396,028).

Technologies for protecting data in asymmetric storage volume
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,540,505) developed by Boyd, James A., Hillsboro, OR, Juenemann, Dale J., North Plains, OR, and Royer, Jr., Robert J., Portland, OR, for “technologies for protecting data in an asymmetric storage volume.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Technologies for protecting data in an asymmetric volume, (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.”

The patent application was filed on September 29, 2017 (15/721,554).

Storage device having improved write uniformity stability
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,528,462) developed by Ramalingam, Anand S., Beverton, OR, for a “storage device having improved write uniformity stability.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.”

The patent application was filed on September 26, 2016 (15/276,696).

Throttling rate at which commands are accepted in storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,521,121) developed by Carlton, David B., Oakland, CA, Guo, Xin, San Jose, CA, and Du, Yu, Santa Clara, CA, for “apparatus, system and method for throttling a rate at which commands are accepted in a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output, (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.”

The patent application was filed on December 29, 2016 (15/394,653).

Multiple storage devices implemented using common connector
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,509,759) developed by Willis, Daniel S., and Constantine, Anthony M., Portland, OR, for “multiple storage devices implemented using a common connector.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.”

The patent application was filed on March 31, 2017 (15/476,882).

Selective caching of erasure coded fragments in distributed storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,503,654) developed by Raghunath, Arun, Hillsboro, OR, Mesnier, Michael P., Scappoose, OR, and Zou, Yi, Portland, OR, for a “selective caching of erasure coded fragments in a distributed storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Methods and apparatus related to framework and/or methodology for selective caching of Erasure Coded fragments in a distributed storage system are described. In one embodiment, a plurality of fragments of a data object are generated. Each of the plurality of fragments is Erasure Coded, (EC) prior to storage at a storage node of a plurality of storage nodes. Each of the plurality of fragments is transmitted with a caching hint to indicate whether that fragment is to be cached at the storage node. Other embodiments are also disclosed and claimed.”

The patent application was filed on September 1, 2016 (15/254,824).

Scrubbing disaggregated storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,503,587) developed by Chagam Reddy, Anjaneya R., Chandler, AZ, Kumar, Mohan J., Aloha, OR, Sen, Sujoy, Portland, OR, and Gohad, Tushar, Phoenix, AZ, for a “scrubbing disaggregated storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Apparatuses, systems and methods are disclosed herein that generally relate to distributed network storage and filesystems, such as Ceph, Hadoop.RTM., or other big data storage environments utilizing resources and/or storage that may be remotely located across a communication link such as a network. More particularly, disclosed are techniques for one or more machines or devices to scrub data on remote resources and/or storage without requiring all or substantially all of the remote data to be read across the communication link in order to scrub it. Some disclosed embodiments discuss having validation be relatively local to storage(s) being scrubbed, and some embodiments discuss only providing to the one or more machines scrubbing data selected results of the relatively local scrubbing over the communication link.”

The patent application was filed on June 30, 2017 (15/639,781).

Performing multi-object transformations on storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,496,335) developed by Khan, Jawad Basit, Cornelius, OR, Li, Peng, and Trika, Sanjeev, Portland, OR, for “method and apparatus for performing multi-object transformations on a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”In one embodiment, a storage device comprises non-volatile storage media, a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media, and a transformation engine to apply the transformation to the first data object and the second data object.”

The patent application was filed on June 30, 2017 (15/639,838).

Configurable flush of data from volatile memory to non-volatile memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (10,496,298) developed by Kandula, Phani Kumar, Bangalore, India, Pillilli, Bharat S., El Dorado Hills, CA, Chemudupati, Suresh, Austin, TX, and Liu, Yi-Feng, Chandler, AZ, for a “configurable flush of data from volatile memory to non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.”

The patent application was filed on December 28, 2017 (15/856,780).