R&D : Aging Capacitor Supported Cache Management Scheme for SSD

IEEE has published, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, an article written by Congming Gao, College of Computer Science, Chongqing University, Chongqing, P.R. China, and also with the University of Pittsburgh, Pennsylvania, USA, Liang Shi, School of Computer Science and Software Engineering, East China Normal University, Shanghai, P.R. China, Qiao Li, Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong, Kai Liu, College of Computer Science, Chongqing University, Chongqing, P.R. China, Chun Jason Xue, Department of Computer Science, City University of Hong Kong, Kowloon, Hong Kong, Jun Yang, and Youtao Zhang, University of Pittsburgh, Pennsylvania, USA.

Abstract: “Solid state drives (SSDs) have been widely adopted in embedded systems, data center and cloud storage due to its well-identified advantages. Inside SSD, random access memory (RAM) is adopted as the built-in cache for achieving better performance. However, due to the volatility characteristic of RAM, data loss may happen when sudden power interrupts. In order to solve this issue, capacitor has been equipped inside emerging SSDs as interim power supplier. But due to the capacitor aging issue, which will result in capacitance decreases over time, there still may exist data loss when power interruption occurs. Once the remaining capacitance drops to the threshold value where all dirty pages in the cache can not be written back to flash memory, data loss happens. To solve the above issue, an efficient cache management scheme for capacitor equipped SSDs is proposed in this work. The basic idea of this scheme is to bound the number of dirty pages in cache within the capability of equipped capacitor. The proposed scheme includes three steps: First, a periodical dirty page budget detection scheme is proposed to acquire the maximal number of dirty pages that can be written back within current capability of equipped capacitor. Second, a smart dirty page synchronizing scheme is proposed during normal run time to bound the number of dirty pages in the cache. Third, when power supply interrupts, an efficient writing back method is applied to further reduce the capacitance consumption of capacitor. Simulation results show that the proposed scheme achieves encouraging improvement on lifetime and performance while power interruption induced data loss is avoided.“