R&D: Tolerance of Deep Neural Network Against Bit Error Rate of NAND Flash Memory

Study effects of flash's bit-error-rate on neural network's weights and prediction accuracy, given that error correction engine is disabled due to power constraint in edge devices.

This is a Press Release edited by StorageNewsletter.com on June 5, 2019 at 2:14 pm

IEEE Xplore has published, in 2019 IEEE International Reliability Physics Symposium (IRPS) proceedings, an article written by Mehedi Hasan, and Biswajit Ray, Electrical and Computer Engineering Department, The University of Alabama, Huntsville, AL, 35899, USA.

Abstract: “Flash memory can store large number of model weights for a deep neural network on edge devices. In this paper, we study the effects of flash’s bit-error-rate on the neural network’s weights and prediction accuracy, given that error correction engine is disabled due to power constraint in edge devices. The reliability experiments on MLC NAND flash show that DNN prediction accuracy remains above the acceptable level in the presence of different NAND reliability issues for the following memory usage: less than five years of data retention, ~100 program-erase cycle, and less than 30k read stress.“