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Qualcomm Assigned Five Patents

Managing information in smart storage, data organization in storage systems using large erasure codes, SRM in virtualized environments, multi-host power controller of flash-memory-based storage device, low-power 5T SRAM with improved stability and reduced bitcell size

Managing information in smart storage
Qualcomm Inc., San Diego, CA, has been assigned a patent (9,942,689) developed by Ganesh, Shriram, Zhu, Xiaomin, San Diego, CA, Ruvalcaba, Jose Alfredo, Winchester, CA, and Berionne, Michele, San Diego, CA, for a “
systems, apparatus, and methods for managing information in a smart storage.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides systems, methods, and apparatus for managing information in a smart storage device. In one aspect a smart storage device is provided that is configured to be coupled to a wireless communications apparatus operating in a wireless communications network. The smart storage device includes a memory configured to store network access information for accessing services of the network. The smart storage device further includes a controller configured to send a message to the wireless communications apparatus including data notifying the wireless communications apparatus of an update to the network access information. The data further includes a command that the wireless communications apparatus suspend an active operation of the wireless communications apparatus and initiate updating information managed by the wireless communications apparatus based on one or more conditions. The updating of the information is based on at least a portion of the updated network access information.

The patent application was filed on March 29, 2016 (15/084,427).

Data organization in storage systems using large erasure codes
Qualcomm Inc., San Diego, CA, has been assigned a patent (9,933,973) developed by Luby, Michael George, Berkeley, CA, and Richardson, Thomas Joseph, South Orange, NJ, for a “
systems and methods for data organization in storage systems using large erasure codes.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods which implement one or more data organization techniques that facilitate efficient access to source data stored by a storage system are disclosed. Data organization techniques implemented according to embodiments are adapted to optimize, (e.g., maximize) input/output efficiency and/or, (e.g., minimize) storage overhead, while maintaining mean time to data loss, repair efficiency, and/or traffic efficiency. Data organization techniques as may be implemented by embodiments include blob based organization techniques, grouped symbols organization techniques, data ordering organization techniques, and combinations thereof.

The patent application was filed on November 30, 2015 (14/954,814).

Storage resource management in virtualized environments
Qualcomm Inc., San Diego, CA, has been assigned a patent (9,891,945) developed by Shacham, Assaf, Zichron Yaakov, Israel, Yahalom, Tom, Maagan Michael, Israel, and Teb, David, Acco, CA, for a “
storage resource management in virtualized environments.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Storage resource management in virtualized environments is provided. In this regard, when receiving a request for accessing a target general purpose partition, (GPP) in a storage device, partition switching circuitry is configured to determine whether the target GPP equals a current GPP that is accessed by a list of existing requests. The partition switching circuitry adds the request into the list of existing requests if the target GPP equals the current GPP. Otherwise, the partition switching circuitry waits for the list of existing requests to be executed on the current GPP before switching to the target GPP to execute the request received from a client. By switching to the target GPP after executing the list of existing commands on the current GPP, it is possible to share a plurality of GPPs among multiple clients in a virtualized environment while maintaining data integrity and security in the storage device.

The patent application was filed on March 21, 2016 (15/075,945).

Multi-host power controller of flash-memory-based storage device
Qualcomm Inc., San Diego, CA, has been assigned a patent (9,881,680) developed by Shacham, Assaf, Zichron Yaakov, Israel, Susman, Lee, Burgata, Israel, and Teb, David, Haifa, Israel, for a “
multi-host power controller, MHPC) of a flash-memory-based storage device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A multi-host power controller, (MHPC) of a flash-memory-based storage device is disclosed. In one aspect, the MHPC receives power mode change requests from each of multiple input/output, (I/O) clients. The MHPC extracts and stores a ‘vote,’ or a requested power mode, from the power mode change requests, and then applies a voting logic to the stored votes to determine whether to transition the flash-memory-based storage device between power modes. If the flash-memory-based storage device is not currently operating in the power mode determined by the MHPC, the MHPC is configured to issue a power mode change command to the flash-memory-based storage device to transition to the determined power mode. In this manner, the MHPC is able to control the power mode of the flash-memory-based storage device while receiving direct power mode change requests from multiple I/O clients.

The patent application was filed on June 2, 2015 (14/728,296).

Low-power 5T SRAM with improved stability and reduced bitcell size
Qualcomm Inc., San Diego, CA, has been assigned a patent (9,875,788) developed by Jung, Seong-Ook, Park, Hyunkook, Seoul, Korea, Song, Seung-Chul, Austin, TX, Abu-Rahma, Mohamed Hassan, Ge, Lixin, Wang, Zhongze, and Beom-Mo Han,, San Diego, CA, for a “
low-power 5T SRAM with improved stability and reduced bitcell size.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A 5 Transistor Static Random Access Memory, (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

The patent application was filed on March 25, 2010 (12/731,668).

 

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