SanDisk 3D Assigned Six Patents

Nonvolatile memory cell without dielectric antifuse
having high- and low-impedance states
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,246,089) developed by Herner, Scott Brad, San Jose, CA, and Walker, Andrew, Mountain View, CA, for a “nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.“

The patent application was filed on December 31, 2013 (14/145,614).

Non-volatile memory having 3D array of read/write elements
with efficient decoding of vertical bit lines and word lines
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,245,629) developed by Samachisa, George, Atherton, CA, Fasoli, Luca, Campbell, CA, Higashitani, Masaaki, and Scheuerlein, Roy Edwin, Cupertino, CA, for a “method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.“

The patent application was filed on October 18, 2013 (14/057,971).

Shared-gate vertical-TFT for vertical bit line array
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,236,122) developed by Yan, Tianhong, Saratoga, CA, Samachisa, George, San Jose, CA, Liu, Tz-yi, Palo Alto, CA, Chen, Tim, Milpitas, CA, and Ratnam, Perumal, Fremont, CA, for a “shared-gate vertical-TFT for vertical bit line array.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A non-volatile storage device comprises: a substrate, a monolithic three dimensional array of memory cells, word lines connected to the memory cells, global bit lines, vertical bit lines connected to the memory cells, and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an ‘on’ condition for the double gated vertically oriented select devices to be activated.“

The patent application was filed on July 24, 2014 (14/340,454).

Memories with cylindrical read/write stacks
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,227,456) developed by Chien, Henry, San Jose, CA, Lee, Yao-Sheng, Tampa, FL, Samachisa, George, and Alsmeier, Johann, San Jose, CA, for a “memories with cylindrical read/write stacks.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.“

The patent application was filed on March 7, 2013 (13/789,375).

Three-dimensional nonvolatile memory
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,214,243) developed by Johnson, Mark G., Los Altos, CA, Lee, Thomas H., Cupertino, CA, Subramanian, Vivek, Menlo Park, CA, Farmwald, Paul Michael, Portola Valley, CA, and Cleeves, James M., Redwood, CA, for a “three-dimensional nonvolatile memory and method of fabrication.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.“

The patent application was filed on May 6, 2014 (14/270,409).

Three-dimensional array of re-programmable non-volatile memory
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (9,190,134) developed by Samachisa, George, Milpitas, CA, for a “three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.“

The patent application was filed on January 13, 2014 (14/153,794).