Semtech Adds Low Power, Low Latency PCIe 3.0 PHY

Semtech Corporation, supplier of analog and mixed-signal semiconductors, announced the addition of a PCIe 3.0 PHY IP Platform offering, part of the Snowbush IP family, optimized for low power and low latency.

Building on 14 PCIe 3.0 specification customer product tape-outs at 40nm, and six PCIe 3.0 specification customers on TSMC 28nm process, this offering provides customers with lowest power and lowest latency, while meeting the reach requirements of compliance for PCIe channels. The PHY provides a differentiated choice of power supplies (1.8V, 2.5V or 3.3V) to support legacy applications and ease of integration.

The low power consumption for both normal and low power state modes, combined with low wake up latencies, enables customers to reduce system power. These features give customers an IP choice when developing PCIe interfaces for the storage, server and HPC markets.

Maintaining the lowest possible power in all operating modes, while maintaining the necessary reach, is of overriding concern when using the PCIe architecture in a server application. Legacy channels can be lossy and often require additional power consumption. Maintaining the power efficiency across different long and short reach channels is challenging. The PHY platform can support both long reach and short reach channels, delivering compliant performance with a power efficiency of less than 7.5pJ/bit in 28nm. As the Snowbush technology moves to 16 FinFET, the power is expected to be reduced by as much as 30%.

Storage applications require low-power across all operating modes and low-latency. Providing fast wake up time in the order of tens of nano-seconds is critical in storage applications. New enhancements to the L1 sub-state have been added to reduce power when the PCI link is idle.

“Semtech’s continued investment into new product offerings helps enable the PCIe ecosystem,” said Al Yanes, PCI-SIG president and chairman. “As a member of PCI-SIG, Semtech produces PCIe 3.0 products that help ensure the continued success of the PCIe 3.0 architecture in the market.”

“This new offering gives our customers IP that is differentiated by its performance, power, and stringent latency requirements,” said Kevin Walsh, WW marketing director, Snowbush IP. “We expect that the 28nm process node will continue to be very active for server and storage, as well as in high-end consumer applications, for some time to come. By providing robust, silicon-proven PHY IP, with significant differentiation for these segments, customers gain both in confidence and in quantifiable performance improvements.“

The PCIe PHY IP supporting 2.5V and 3.3V is available. The 1.8V will be available in Q3. Pricing depends on configuration and the number of instantiations in a design.