IT Press Tour 70: ScaleFlux

For the 2nd times, ScaleFlux joined The IT Press Tour and it gave us the chance to get a company and product update from Hao Zhong, CEO, and its executives, Pichai Balaji, VP product marketing, and Saeed Raja, VP, products, as many changes have happened within the company and on the market.Starting in 2014 and based in Milpitas, CA, the company is a pioneer in computational storage with transparent inline compression. It was the case with the early CSD product family from 1000 to 5000 in 2024 with PCIe Gen5. In parallel, the company built an in-house IP portfolio covering NVMe controllers, a NAND PHY interface, error correction, in-band DRAM ECC and write-reduction technology. It has also moved from making drives to selling silicon with several following examples:

• SFX3016 (2021), FX5016 (2023), FC5116 (2025) and FC5104: PCIe 4.0 and 5.0 SSD controllers
• FC6116: PCIe 6.0 SSD controller, launched in 2026 for the company’s tenth anniversary
• MC500: CXL 3.1 memory controller, launched in 2024
• MC600: CXL 3.2 / PCIe 6.0 memory controller

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But as the market evolved fast and put a strong pressure on the infrastructure with the recent famous “Memory Wall” notion, the firm has adapted its vision and adopted a new one: “the silicon foundation that moves AI data at the speed of compute, from memory, through storage into context”. Its mission is to remove data-movement bottlenecks across compute, memory and storage.

Balaji identified 3 challenges in today’s fast growing IT AI infrastructure:

1. GPUs wait too long for data. ScaleFlux says DDR5 is 37 to 40 times slower than GPU memory transactions, and a PCIe Gen6 SSD is 750 to 800 times slower, at about 2 ms response time. The answer it proposes is scalable memory and storage tiers that can keep GPUs busy
2. A supply gap in SSDs and memory. ScaleFlux’s illustrative estimate for 2027 has about 94% of memory and storage demand coming from AI data centers and enterprise SSDs, 500 to 600EB of enterprise NAND across 55 to 60M drives. DDR5 accounts for about 5% and GPU HBM for less than 1%. Its conclusion is that the memory supply chain needs to be managed efficiently
3. One size doesn’t fit all. AI compute nodes need 2 to 16TB at high bandwidth, training needs 8 to 30TB with fast checkpointing, inference caches need 16 to 60TB with high IOPS and low latency, and AI storage needs 30 to 256TB. Enterprise boot drives need 512 GB to 4TB

To address these, ScaleFlux introduced a “Lego” model for building SSDs and CXL modules.
ScaleFlux’s answer is to sell controllers, firmware and reference designs as building blocks that can be assembled and manufactured at scale. Customers can choose:

• any NAND or DRAM vendor
• ScaleFlux’s turnkey firmware, custom firmware, or their own
• ScaleFlux’s manufacturing partners or their own contract manufacturer

In other words, ScaleFlux is really component agnostic. The partner program offers validated full-stack solutions in E1.S/L, E3.S/L and U.2/U.3 form factors at any capacity, with a resilient supply chain and global support. ScaleFlux pitches this flexibility as the route to the lowest total cost of ownership while memory supplies are tight.

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To detail products lines, we wish to insist on 2 specific ones: one related to NVMe and the second dedicate to CXL.

FC6116 (PCIe 6.0 NVMe controller)

• 16 channels, up to 256 dies per channel, TLC/QLC/SLC NAND
• Up to 28 GB/s read and 25 GB/s write, 7M random read IOPS and more than 1M sustained random write IOPS, at about 9W
• Capacities from 512 GB to 256TB, NVMe 2.3 and OCP 2.6
• Security: AES-XTS-256, OCP Caliptra 2.0, the S.A.F.E. framework, firmware attestation, and CNSA 2.0 post-quantum cryptography
• Supports NVIDIA’s CMX context memory platform and more than 200 Flexible Data Placement (FDP) streams per SSD for KV cache workloads

The FC5116 (PCIe 5.0) is in production with ScaleFlux’s write-reduction technology.

MC600 (CXL 3.2 Type 3 memory controller)

• PCIe 6.0, about 60 ns round-trip latency at queue depth 1, under 9W
• Supports both DDR5 and DDR4, up to 2TB, so customers can reuse existing DDR4
• Server-grade RAS, transparent compression for effective capacity gains, and the same security stack as the FC6116
• Available as add-in cards or EDSFF E3.S

ScaleFlux positions CXL memory as a new “G2.5” tier between HBM/DRAM and SSD, moving from expansion to pooling to tiering. Its goal is “more usable memory per DRAM dollar” for hyperscalers.

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The go-to-market strategy was also a key point of this presentation as SCaleFlux wish to be open and address a vast majority of needs.

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Its ecosystem runs from TSMC and packaging partners to CPU, GPU, NAND and DRAM suppliers, server makers and AI software vendors.

And to conclude, ScaleFlux lists five reasons it wins: a flexible business model, independence from any memory vendor, freedom in manufacturing, in-house silicon IP and faster time to market. It maps them onto the three challenges: re-architect the data path for scale, make DRAM and NAND sourcing accessible to more customers, and build tiered solutions to order from one platform.