JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap

JEDEC Solid State Technology Association announced milestones from its JC-40 and JC-45 Committees for Logic and DRAM Modules: the publication of a new DDR5 multiplexed rank data buffer (MDB) standard; progress toward a multiplexed rank registering clock driver (MRCD) standard; and continued work on the DDR5 multiplexed rank DIMM (MRDIMM)  Gen2 roadmap to enable higher-bandwidth DDR5 MRDIMM designs.

• Published: JESD82-552 (DDR5MDB02) Multiplexed Rank Data Buffer
• Expected soon: JESD82-542 (DDR5MRCD02) Multiplexed Rank Registering Clock Driver
• In progress: MRDIMM Gen2 module standard nearing completion
• In development: Gen2 DDR5 MRDIMM raw card designs targeting 12,800MT/s and MRDIMM Gen3 module standard development, with the underlying memory interface logic nearing finalization

Published:JEDEC has published JESD82-552: DDR5MDB02 Multiplexed Rank Data Buffer, now available for download from the JEDEC website. The standard defines next-gen data buffer functionality for multiplexed rank DIMM architectures, supporting robust operation as module bandwidth scales.

Expected soon:
JESD82-542: DDR5 Multiplexed Rank Registering Clock Driver (DDR5MRCD02) is expected to be published in the near future. This forthcoming standard is intended to further strengthen signal integrity and timing control in DDR5 MRDIMM module designs, complementing JESD82-552.

In progress:
The JC-45 Committee is nearing completion of its MRDIMM Gen2 standard, advancing high-performance memory module design to meet increasing bandwidth and system-level efficiency requirements for next-generation computing platforms.

In development:
The committee is also developing second-generation DDR5 MRDIMM Gen2 raw card designs targeting 12,800MT/s, underscoring JEDEC’s commitment to enabling higher data rates and scalable memory solutions for data-intensive applications.  JC-45 is also looking ahead to the development of the MRDIMM Gen3 standard.